參數(shù)資料
型號: CY7C1380C-167AI
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: DRAM
英文描述: 18-Mb (512K x 36/1M x 18) Pipelined SRAM
中文描述: 512K X 36 CACHE SRAM, 3.4 ns, PQFP100
封裝: 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
文件頁數(shù): 18/36頁
文件大?。?/td> 788K
代理商: CY7C1380C-167AI
CY7C1380C
CY7C1382C
Document #: 38-05237 Rev. *D
Page 18 of 36
3.3V TAP AC Test Conditions
Input pulse levels........ ........................................V
SS
to 3.3V
Input rise and fall times...................... ..............................1ns
Input timing reference levels...........................................1.5V
Output reference levels...................................................1.5V
Test load termination supply voltage...............................1.5V
3.3V TAP AC Output Load Equivalent
2.5V TAP AC Test Conditions
Input pulse levels...............................................
V
SS
to 2.5V
Input rise and fall time ......................................................1ns
Input timing reference levels.........................................1.25V
Output reference levels ................................................1.25V
Test load termination supply voltage ............................1.25V
2.5V TAP AC Output Load Equivalent
Note:
11.All voltages referenced to V
SS
(GND).
TDO
1.5V
20pF
Z = 50
50
TDO
1.25V
20pF
Z = 50
50
TAP DC Electrical Characteristics And Operating Conditions
(0°C < TA < +70°C; Vdd = 3.3V ±0.165V unless otherwise noted)
[11]
PARAMETER
DESCRIPTION
TEST CONDITIONS
MIN
MAX
UNITS
V
OH1
Output HIGH Voltage I
OH
= -4.0 mA,V
DDQ
= 3.3V
I
OH
= -1.0 mA,V
DDQ
= 2.5V
Output HIGH Voltage I
OH
= -100 μA
2.4
V
2.0
V
V
OH2
V
DDQ
= 3.3V
V
DDQ
= 2.5V
V
DDQ
= 3.3V
V
DDQ
= 2.5V
V
DDQ
= 3.3V
V
DDQ
= 2.5V
V
DDQ
= 3.3V
V
DDQ
= 2.5V
V
DDQ
= 3.3V
V
DDQ
= 2.5V
2.9
V
2.1
V
V
OL1
Output LOW Voltage
I
OL
= 8.0 mA
0.4
V
0.4
V
V
OL2
Output LOW Voltage
I
OL
= 100 μA
0.2
V
0.2
V
V
IH
Input HIGH Voltage
2.0
V
DD
+ 0.3
V
DD
+ 0.3
0.8
V
1.7
V
V
IL
Input LOW Voltage
-0.3
V
-0.3
0.7
V
I
X
Input Load Current
GND < V
IN
< V
DDQ
-5
5
μA
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