參數(shù)資料
型號(hào): CY7C1380C-167AI
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: DRAM
英文描述: 18-Mb (512K x 36/1M x 18) Pipelined SRAM
中文描述: 512K X 36 CACHE SRAM, 3.4 ns, PQFP100
封裝: 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
文件頁數(shù): 28/36頁
文件大?。?/td> 788K
代理商: CY7C1380C-167AI
CY7C1380C
CY7C1382C
Document #: 38-05237 Rev. *D
Page 28 of 36
Switching Waveforms
Read Cycle Timing
[21]
Notes:
21.On this diagram, when CE is LOW: CE
is LOW, CE
is HIGH and CE
is LOW. When CE is HIGH: CE
1
is HIGH or CE
2
is LOW or CE
3
is HIGH.
22.Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW
X
LOW.
tCYC
tCL
CLK
ADSP
tADH
tADS
ADDRESS
tCH
OE
ADSC
CE
tAH
tAS
A1
tCEH
tCES
GW, BWE,
BWx
Data Out (Q)
High-Z
tCLZ
tDOH
tCO
ADV
tOEHZ
tCO
Single READ
BURST READ
tOEV
tOELZ
tCHZ
ADV
suspends
burst.
Burst wraps around
to its initial state
tADVH
tADVS
tWEH
tWES
tADH
tADS
Q(A2)
Q(A2 + 1)
Q(A2 + 2)
Q(A1)
Q(A2)
Q(A2 + 1)
Q(A2 + 3)
A2
A3
Deselect
cycle
Burst continued with
new base address
DON’T CARE
UNDEFINED
相關(guān)PDF資料
PDF描述
CY7C1380C-167BGC 18-Mb (512K x 36/1M x 18) Pipelined SRAM
CY7C1380C-167BGI 18-Mb (512K x 36/1M x 18) Pipelined SRAM
CY7C1380C-200AC 18-Mb (512K x 36/1M x 18) Pipelined SRAM
CY7C1380C-200BGC 18-Mb (512K x 36/1M x 18) Pipelined SRAM
CY7C1380C-250AC 18-Mb (512K x 36/1M x 18) Pipelined SRAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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