參數(shù)資料
型號： CY7C1380C-167AI
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： DRAM
英文描述： 18-Mb (512K x 36/1M x 18) Pipelined SRAM
中文描述： 512K X 36 CACHE SRAM, 3.4 ns, PQFP100
封裝： 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
文件頁數(shù)： 13/36頁
文件大?。?/td> 788K
代理商： CY7C1380C-167AI
CY7C1380C
CY7C1382C
Document #: 38-05237 Rev. *D
Page 13 of 36
Asserting ADV LOW at clock rise will automatically increment
the burst counter to the next address in the burst sequence.
Both Read and Write burst operations are supported.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE
, CE
, CE
, ADSP, and ADSC must
remain inactive for the duration of t
ZZREC
after the ZZ input
returns LOW
.
Interleaved Burst Address Table
(MODE = Floating or V
DD
)
First
Address
A1: A0
00
01
10
11
Linear Burst Address Table
(MODE = GND)
Second
Address
A1: A0
01
00
11
10
Third
Address
A1: A0
10
11
00
01
Fourth
Address
A1: A0
11
10
01
00
First
Address
A1: A0
00
01
10
11
Second
Address
A1: A0
01
10
11
00
Third
Address
A1: A0
10
11
00
01
Fourth
Address
A1: A0
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
I
DDZZ
t
ZZS
t
ZZREC
t
ZZI
t
RZZI
Description
Test Conditions
ZZ > V
DD
– 0.2V
ZZ > V
DD
– 0.2V
ZZ < 0.2V
This parameter is sampled
This parameter is sampled
Min.
Max.
60mA
2t
CYC
Unit
mA
ns
ns
ns
ns
Snooze mode standby current
Device operation to ZZ
ZZ recovery time
ZZ Active to snooze current
ZZ Inactive to exit snooze current
2t
CYC
2t
CYC
0
Truth Table
[ 3, 4, 5, 6, 7, 8]
Operation
Add. Used
None
None
None
None
None
None
External
External
External
External
External
Next
Next
Next
CE
1
H
L
L
L
L
X
L
L
L
L
L
X
X
H
CE
2
X
L
X
L
X
X
H
H
H
H
H
X
X
X
CE
3
X
X
H
X
H
X
L
L
L
L
L
X
X
X
ZZ
L
L
L
L
L
H
L
L
L
L
L
L
L
L
ADSP
X
L
L
H
H
X
L
L
H
H
H
H
H
X
ADSC
L
X
X
L
L
X
X
X
L
L
L
H
H
H
ADV
X
X
X
X
X
X
X
X
X
X
X
L
L
L
WRITE
X
X
X
X
X
X
X
X
L
H
H
H
H
H
OE CLK
X
X
X
X
X
X
L
H
X
L
H
L
H
L
DQ
Deselect Cycle,Power Down
Deselect Cycle,Power Down
Deselect Cycle,Power Down
Deselect Cycle,Power Down
Deselect Cycle,Power Down
Snooze Mode,Power Down
READ Cycle, Begin Burst
READ Cycle, Begin Burst
WRITE Cycle, Begin Burst
READ Cycle, Begin Burst
READ Cycle, Begin Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
L-H
L-H
L-H
L-H
L-H
X
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
Tri-State
Tri-State
Tri-State
Tri-State
Tri-State
Tri-State
Q
Tri-State
D
Q
Tri-State
Q
Tri-State
Q
相關(guān)PDF資料
PDF描述
CY7C1380C-167BGC 18-Mb (512K x 36/1M x 18) Pipelined SRAM
CY7C1380C-167BGI 18-Mb (512K x 36/1M x 18) Pipelined SRAM
CY7C1380C-200AC 18-Mb (512K x 36/1M x 18) Pipelined SRAM
CY7C1380C-200BGC 18-Mb (512K x 36/1M x 18) Pipelined SRAM
CY7C1380C-250AC 18-Mb (512K x 36/1M x 18) Pipelined SRAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CY7C1380C-167BGC 制造商:Cypress Semiconductor 功能描述:
CY7C1380C-167BGCT 制造商:Cypress Semiconductor 功能描述:
CY7C1380C-167BZC 制造商:Cypress Semiconductor 功能描述:SRAM SYNC SGL 3.3V 18MBIT 512KX36 3.4NS 165FBGA - Bulk
CY7C1380C-167BZI 功能描述:IC SRAM 512KX36 SYNC 165-FBGA RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 格式 - 存儲(chǔ)器:EEPROMs - 串行 存儲(chǔ)器類型:EEPROM 存儲(chǔ)容量:4K (512 x 8) 速度:400kHz 接口:I²C，2 線串口 電源電壓:2.7 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-SOIC（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:8-MFP 包裝:帶卷 (TR)
CY7C1380C-200AC 制造商:Rochester Electronics LLC 功能描述:16MB (512KX36) 3.3V SYNC-PIPE (SINGLE CYCLE DESELECT) SRAM - Bulk
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