參數(shù)資料
型號： CY7C1380C-167AI
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： DRAM
英文描述： 18-Mb (512K x 36/1M x 18) Pipelined SRAM
中文描述： 512K X 36 CACHE SRAM, 3.4 ns, PQFP100
封裝： 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
文件頁數(shù)： 14/36頁
文件大?。?/td> 788K
代理商： CY7C1380C-167AI
CY7C1380C
CY7C1382C
Document #: 38-05237 Rev. *D
Page 14 of 36
READ Cycle, Continue Burst
WRITE Cycle, Continue Burst
WRITE Cycle, Continue Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
WRITE Cycle,Suspend Burst
WRITE Cycle,Suspend Burst
Next
Next
Next
Current
Current
Current
Current
Current
Current
H
X
H
X
X
H
H
X
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
L
L
L
X
H
X
H
H
X
X
H
X
H
H
H
H
H
H
H
H
H
L
L
L
H
H
H
H
H
H
H
L
L
H
H
H
H
L
L
H
X
X
L
H
L
H
X
X
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
Tri-State
D
D
Q
Tri-State
Q
Tri-State
D
D
Notes:
3. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.
4. WRITE = L when any one or more Byte Write enable signals and BWE = L or GW= L. WRITE = H when all Byte write enable signals , BWE, GW = H.
5. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
6. CE
1
, CE
2
, and CE
3
are available only in the TQFP package. BGA package has only 2 chip selects CE
1
and CE
2
.
7. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW
. Writes may occur only on subsequent clocks
after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state. OE is a
8. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are Tri-State when OE is
inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).
Truth Table for Read/Write
[5]
Function (CY7C1380C)
GW
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
BWE
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
BW
D
X
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
X
BW
C
X
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
X
BW
B
X
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
X
BW
A
X
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
X
Read
Read
Write Byte A – ( DQ
A
and DQP
A
)
Write Byte B – ( DQ
B
and DQP
B
)
Write Bytes B, A
Write Byte C – ( DQ
C
and DQP
C
)
Write Bytes C, A
Write Bytes C, B
Write Bytes C, B, A
Write Byte D – ( DQ
D
and DQP
D
)
Write Bytes D, A
Write Bytes D, B
Write Bytes D, B, A
Write Bytes D, C
Write Bytes D, C, A
Write Bytes D, C, B
Write All Bytes
Write All Bytes
Truth Table for Read/Write
[5]
Function (CY7C1382C)
GW
H
H
H
H
H
H
L
BWE
H
L
L
L
L
L
X
BW
B
X
H
H
L
L
L
X
BW
A
X
H
L
H
L
L
X
Read
Read
Write Byte A – ( DQ
A
and DQP
A
)
Write Byte B – ( DQ
B
and DQP
B
)
Write Bytes B, A
Write All Bytes
Write All Bytes
Truth Table
[ 3, 4, 5, 6, 7, 8]
Operation
Add. Used
CE
1
CE
2
CE
3
ZZ
ADSP
ADSC
ADV
WRITE
OE CLK
DQ
相關(guān)PDF資料
PDF描述
CY7C1380C-167BGC 18-Mb (512K x 36/1M x 18) Pipelined SRAM
CY7C1380C-167BGI 18-Mb (512K x 36/1M x 18) Pipelined SRAM
CY7C1380C-200AC 18-Mb (512K x 36/1M x 18) Pipelined SRAM
CY7C1380C-200BGC 18-Mb (512K x 36/1M x 18) Pipelined SRAM
CY7C1380C-250AC 18-Mb (512K x 36/1M x 18) Pipelined SRAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CY7C1380C-167BGC 制造商:Cypress Semiconductor 功能描述:
CY7C1380C-167BGCT 制造商:Cypress Semiconductor 功能描述:
CY7C1380C-167BZC 制造商:Cypress Semiconductor 功能描述:SRAM SYNC SGL 3.3V 18MBIT 512KX36 3.4NS 165FBGA - Bulk
CY7C1380C-167BZI 功能描述:IC SRAM 512KX36 SYNC 165-FBGA RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 格式 - 存儲器:EEPROMs - 串行 存儲器類型:EEPROM 存儲容量:4K (512 x 8) 速度:400kHz 接口:I²C，2 線串口 電源電壓:2.7 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-SOIC（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:8-MFP 包裝:帶卷 (TR)
CY7C1380C-200AC 制造商:Rochester Electronics LLC 功能描述:16MB (512KX36) 3.3V SYNC-PIPE (SINGLE CYCLE DESELECT) SRAM - Bulk
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