參數(shù)資料
型號： CY7C1380C-167AI
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： DRAM
英文描述： 18-Mb (512K x 36/1M x 18) Pipelined SRAM
中文描述： 512K X 36 CACHE SRAM, 3.4 ns, PQFP100
封裝： 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
文件頁數(shù)： 27/36頁
文件大?。?/td> 788K
代理商： CY7C1380C-167AI
CY7C1380C
CY7C1382C
Document #: 38-05237 Rev. *D
Page 27 of 36
Switching Characteristics
Over the Operating Range
[19, 20]
Parameter
t
POWER
Clock
t
CYC
t
CH
t
CL
Output Times
t
CO
t
DOH
t
CLZ
t
CHZ
t
OEV
t
OELZ
t
OEHZ
Setup Times
t
AS
t
ADS
Description
250 MHz
Min. Max
1
225 MHz
200 MHz
167 MHz
Min.
1
133 MHz
Unit
ms
Max Min.
Max
V
DD
(Typical) to the first Access
[15]
1
1
1
Clock Cycle Time
Clock HIGH
Clock LOW
4.0
1.7
1.7
4.4
2.0
2.0
5
6
7.5
2.5
2.5
ns
ns
ns
2.0
2.0
2.2
2.2
Data Output Valid After CLK Rise
Data Output Hold After CLK Rise
Clock to Low-Z
[16, 17, 18]
Clock to High-Z
[16, 17, 18]
OE LOW to Output Valid
OE LOW to Output Low-Z
[16, 17, 18]
OE HIGH to Output High-Z
[16, 17, 18]
2.6
2.8
3.0
3.4
4.2
ns
ns
ns
ns
ns
ns
ns
1.0
1.0
1.0
1.0
1.3
1.3
1.3
1.3
1.3
1.3
2.6
2.6
2.8
2.8
3.0
3.0
3.4
3.4
3.4
4.2
0
0
0
0
0
2.6
2.8
3.0
3.4
4.0
Address Set-up Before CLK Rise
ADSC, ADSP Set-up Before CLK
Rise
ADV Set-up Before CLK Rise
GW, BWE, BW
X
Set-up Before CLK
Rise
Data Input Set-up Before CLK Rise
Chip Enable Set-Up Before CLK Rise
1.2
1.2
1.4
1.4
1.4
1.4
1.5
1.5
1.5
1.5
ns
ns
t
ADVS
t
WES
1.2
1.2
1.4
1.4
1.4
1.4
1.5
1.5
1.5
1.5
ns
ns
t
DS
t
CES
Hold Times
t
AH
t
ADH
t
ADVH
t
WEH
t
DH
t
CEH
Shaded areas contain advance information.
1.2
1.2
1.4
1.4
1.4
1.4
1.5
1.5
1.5
1.5
ns
ns
Address Hold After CLK Rise
ADSP , ADSC Hold After CLK Rise
ADV Hold After CLK Rise
GW,BWE, BW
X
Hold After CLK Rise
Data Input Hold After CLK Rise
Chip Enable Hold After CLK Rise
0.3
0.3
0.3
0.3
0.3
0.3
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
Notes:
15.This part has a voltage regulator internally; t
POWER
is the time that the power needs to be supplied above V
DD
( minimum) initially before a read or write operation
can be initiated.
16.t
, t
,t
, and t
are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
17.At any given voltage and temperature, t
is less than t
and t
is less than t
to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions
18.This parameter is sampled and not 100% tested.
19.Timing reference level is 1.5V when V
= 3.3V and is 1.25V when V
DDQ
= 2.5V.
20.Test conditions shown in (a) of AC Test Loads unless otherwise noted.
相關(guān)PDF資料
PDF描述
CY7C1380C-167BGC 18-Mb (512K x 36/1M x 18) Pipelined SRAM
CY7C1380C-167BGI 18-Mb (512K x 36/1M x 18) Pipelined SRAM
CY7C1380C-200AC 18-Mb (512K x 36/1M x 18) Pipelined SRAM
CY7C1380C-200BGC 18-Mb (512K x 36/1M x 18) Pipelined SRAM
CY7C1380C-250AC 18-Mb (512K x 36/1M x 18) Pipelined SRAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CY7C1380C-167BGC 制造商:Cypress Semiconductor 功能描述:
CY7C1380C-167BGCT 制造商:Cypress Semiconductor 功能描述:
CY7C1380C-167BZC 制造商:Cypress Semiconductor 功能描述:SRAM SYNC SGL 3.3V 18MBIT 512KX36 3.4NS 165FBGA - Bulk
CY7C1380C-167BZI 功能描述:IC SRAM 512KX36 SYNC 165-FBGA RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 格式 - 存儲(chǔ)器:EEPROMs - 串行 存儲(chǔ)器類型:EEPROM 存儲(chǔ)容量:4K (512 x 8) 速度:400kHz 接口:I²C，2 線串口 電源電壓:2.7 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-SOIC（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:8-MFP 包裝:帶卷 (TR)
CY7C1380C-200AC 制造商:Rochester Electronics LLC 功能描述:16MB (512KX36) 3.3V SYNC-PIPE (SINGLE CYCLE DESELECT) SRAM - Bulk
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