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參數資料
| 型號： | CY7C1356CV25-225BGC |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 9-Mbit ( 256K x 36/512K x 18 ) Pipelined SRAM with NoBL-TM Architecture |
| 中文描述： | 9兆位（256 × 36/512K × 18）流水線的SRAM的總線延遲，TM架構 |
| 文件頁數： | 9/25頁 |
| 文件大?。?/td> | 353K |
| 代理商： | CY7C1356CV25-225BGC |
PRELIMINARY
CY7C1354CV25
CY7C1356CV25
Document #: 38-05537 Rev. *B
Page 9 of 25
IEEE 1149.1 Serial Boundary Scan (JTAG)
The CY7C1354CV25/CY7C1356CV25 incorporates a serial
boundary scan test access port (TAP) in the BGA package
only. The TQFP package does not offer this functionality. This
part operates in accordance with IEEE Standard 1149.1-1900,
but doesn’t have the set of functions required for full 1149.1
compliance. These functions from the IEEE specification are
excluded because their inclusion places an added delay in the
critical speed path of the SRAM. Note the TAP controller
functions in a manner that does not conflict with the operation
of other devices using 1149.1 fully compliant TAPs. The TAP
operates using JEDEC-standard 2.5V I/O logic levels.
The CY7C1354CV25/CY7C1356CV25 contains a TAP
controller, instruction register, boundary scan register, bypass
register, and ID register.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied
LOW(V
SS
) to prevent clocking of the device. TDI and TMS are
internally pulled up and may be unconnected. They may alter-
nately be connected to V
DD
through a pull-up resistor. TDO
should be left unconnected. Upon power-up, the device will
come up in a reset state which will not interfere with the
operation of the device.
Note:
9. Table only lists a partial listing of the byte write combinations. Any combination of BW
X
is valid. Appropriate write will be done based on which byte write is active.
Partial Write Cycle Description
[2, 3, 4, 9]
Function (CY7C1354CV25)
WE
H
L
BW
d
X
H
BW
c
X
H
BW
b
X
H
BW
a
X
H
Read
Write
–No bytes written
Write Byte a–
(DQ
a
and DQP
a)
Write Byte b – (DQ
b
and
DQP
b)
Write Bytes b, a
Write Byte c –
(DQ
c
and DQP
c)
Write Bytes c, a
Write Bytes c, b
Write Bytes c, b, a
Write Byte d –
(DQ
d
and DQP
d)
Write Bytes d, a
Write Bytes d, b
Write Bytes d, b, a
Write Bytes d, c
Write Bytes d, c, a
Write Bytes d, c, b
Write All Bytes
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
Partial Write Cycle Description
[2, 3, 4, 9]
Function (CY7C1356CV25)
WE
H
L
L
L
L
BW
b
x
H
H
L
L
BW
a
x
H
L
H
L
Read
Write – No Bytes Written
Write Byte a
(DQ
a
and
DQP
a)
Write Byte b – (DQ
b
and DQP
b)
Write Both Bytes
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相關代理商/技術參數 |
參數描述 |
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| CY7C1356CV25-250AXC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C1356S-166AXC | 功能描述:IC SRAM 9MB SYNC 100-TQFP RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:1,000 系列:- 格式 - 存儲器:EEPROMs - 串行 存儲器類型:EEPROM 存儲容量:4K (512 x 8) 速度:400kHz 接口:I²C，2 線串口 電源電壓:2.7 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-SOIC（0.173"，4.40mm 寬） 供應商設備封裝:8-MFP 包裝:帶卷 (TR) |
| CY7C1356S-166AXI | 功能描述:IC SRAM 9MB SYNC 100-TQFP RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:1,000 系列:- 格式 - 存儲器:EEPROMs - 串行 存儲器類型:EEPROM 存儲容量:4K (512 x 8) 速度:400kHz 接口:I²C，2 線串口 電源電壓:2.7 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-SOIC（0.173"，4.40mm 寬） 供應商設備封裝:8-MFP 包裝:帶卷 (TR) |
| CY7C1356S-166BGC | 功能描述:IC SRAM 512KX18 NOBL 119-BGA RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:1,000 系列:- 格式 - 存儲器:EEPROMs - 串行 存儲器類型:EEPROM 存儲容量:4K (512 x 8) 速度:400kHz 接口:I²C，2 線串口 電源電壓:2.7 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-SOIC（0.173"，4.40mm 寬） 供應商設備封裝:8-MFP 包裝:帶卷 (TR) |
| CY7C1356SV25-166AXC | 功能描述:靜態(tài)隨機存取存儲器 9-Mbit Pipelined 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
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