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參數(shù)資料
| 型號： | CY7C1356CV25-225BGC |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 9-Mbit ( 256K x 36/512K x 18 ) Pipelined SRAM with NoBL-TM Architecture |
| 中文描述： | 9兆位（256 × 36/512K × 18）流水線的SRAM的總線延遲，TM架構(gòu) |
| 文件頁數(shù)： | 13/25頁 |
| 文件大?。?/td> | 353K |
| 代理商： | CY7C1356CV25-225BGC |
PRELIMINARY
CY7C1354CV25
CY7C1356CV25
Document #: 38-05537 Rev. *B
Page 13 of 25
2.5V TAP AC Test Conditions
Input pulse levels
........................................ V
SS
to 2.5V
Input rise and fall time .................................................... 1 ns
Input timing reference levels ........................................1.25V
Output reference levels ................................................1.25V
Test load termination supply voltage.............................1.25V
2.5V TAP AC Output Load Equivalent
TDO
1.25V
20pF
Z = 50
50
TAP DC Electrical Characteristics And Operating Conditions
(0°C < TA < +70°C; Vdd = 2.5V ±0.125V unless otherwise noted)
[13]
Parameter
V
OH1
V
OH2
V
OL1
V
OL2
V
IH
V
IL
I
X
Description
Output HIGH Voltage
Test Conditions
Min.
2.0
Max.
Unit
V
I
OH
= -1.0 mA, V
DDQ
= 2.5V
I
OH
= -100 μA,V
DDQ
= 2.5V
I
OL
= 8.0 mA, V
DDQ
= 2.5V
I
OL
= 100 μA
Output HIGH Voltage
2.1
V
Output LOW Voltage
0.4
V
Output LOW Voltage
V
DDQ
= 2.5V
V
DDQ
= 2.5V
V
DDQ
= 2.5V
0.2
V
Input HIGH Voltage
1.7
V
DD
+ 0.3
0.7
V
Input LOW Voltage
-0.3
V
Input Load Current
GND < V
IN
< V
DDQ
-5
5
μA
Identification Register Definitions
Instruction Field
Revision Number (31:29)
Cypress Device ID (28:12)
Cypress JEDEC ID (11:1)
ID Register Presence (0)
CY7C1354CV25
000
01011001000100110
00000110100
1
CY7C1356CV25
000
01011001000010110 Reserved for future use.
00000110100
Allows unique identification of SRAM vendor.
1
Indicate the presence of an ID register.
Description
Reserved for version number.
Scan Register Sizes
Register Name
Bit Size
3
1
32
69
69
Instruction
Bypass
ID
Boundary Scan Order (119-ball BGA package)
Boundary Scan Order (165-ball fBGA package)
Identification Codes
Instruction
EXTEST
Code
000
Description
Captures the Input/Output ring contents. Places the boundary scan register between the TDI and
TDO. Forces all SRAM outputs to High-Z state.
Loads the ID register with the vendor ID code and places the register between TDI and TDO. This
operation does not affect SRAM operation.
Captures the Input/Output contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a High-Z state.
Do Not Use: This instruction is reserved for future use.
Captures the Input/Output ring contents. Places the boundary scan register between TDI and TDO.
Does not affect the SRAM operation.
IDCODE
001
SAMPLE Z
010
RESERVED
SAMPLE/PRELOAD
011
100
Note:
13.All voltages referenced to V
SS
(GND).
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