參數(shù)資料
型號(hào)： CY7C1356CV25-225BGC
廠商： Cypress Semiconductor Corp.
英文描述： 9-Mbit ( 256K x 36/512K x 18 ) Pipelined SRAM with NoBL-TM Architecture
中文描述： 9兆位（256 × 36/512K × 18）流水線的SRAM的總線延遲，TM架構(gòu)
文件頁(yè)數(shù)： 16/25頁(yè)
文件大?。?/td> 353K
代理商： CY7C1356CV25-225BGC
PRELIMINARY
CY7C1354CV25
CY7C1356CV25
Document #: 38-05537 Rev. *B
Page 16 of 25
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage on V
DD
Relative to GND........–0.5V to +3.6V
DC to Outputs in Three-State.............. –0.5V to V
DDQ
+ 0.5V
DC Input Voltage....................................–0.5V to V
DD
+ 0.5V
Electrical Characteristics
Over the Operating Range
[14, 15]
Current into Outputs (LOW).........................................20 mA
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current.................................................... > 200 mA
Operating Range
Range
Commercial
Industrial
Ambient Temperature
0°C to +70°C
–40°C to +85°C
V
DD
/
V
DDQ
2.5V + 5%
Parameter
V
DD
V
DDQ
V
OH
V
OL
V
IH
V
IL
I
X
Description
Power Supply Voltage
I/O Supply Voltage
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
[14]
Input Load
Input Current of MODE Input = V
SS
Test Conditions
Min.
2.375
2.375
2.0
Max.
2.625
V
DD
Unit
V
V
V
V
V
V
μ
A
μ
A
μ
A
μ
A
μ
A
μ
A
mA
mA
mA
mA
mA
mA
V
DD
= Min., I
OH
=
1.0 mA
V
DD
= Min., I
OL
= 1.0 mA
V
DDQ
= 2.5V
V
DDQ
= 2.5V
GND
≤
V
I
≤
V
DDQ
0.4
1.7
–0.3
–5
–30
V
DD
+ 0.3V
0.7
5
Input = V
DD
Input = V
SS
Input = V
DD
5
Input Current of ZZ
–5
30
5
250
220
180
130
120
110
I
OZ
I
DD
Output Leakage Current GND
≤
V
I
≤
V
DD,
Output Disabled
V
DD
Operating Supply
V
DD
= Max., I
OUT
= 0 mA,
f = f
MAX
= 1/t
CYC
–5
4.4-ns cycle, 225 MHz
5-ns cycle, 200 MHz
6-ns cycle, 167 MHz
4.4-ns cycle, 225 MHz
5-ns cycle, 200 MHz
6-ns cycle, 167 MHz
I
SB1
Automatic CE
Power-down
Current—TTL Inputs
Max. V
DD
, Device Deselected,
V
IN
≥
V
IH
or V
IN
≤
V
IL
, f = f
MAX
=
1/t
CYC
I
SB2
Automatic CE
Power-down
Current—CMOS Inputs
Automatic CE
Power-down
Current—CMOS Inputs
Max. V
DD
, Device Deselected,
V
IN
≤
0.3V or V
IN
> V
DDQ
0.3V,
f = 0
Max. V
DD
, Device Deselected,
V
IN
≤
0.3V or V
IN
> V
DDQ
0.3V,
f = f
MAX
= 1/t
CYC
All speed grades
35
mA
I
SB3
4.4-ns cycle, 225 MHz
5-ns cycle, 200 MHz
6-ns cycle, 167 MHz
120
110
100
mA
mA
mA
I
SB4
Automatic CE
Power-down
Current—TTL Inputs
Max. V
DD
, Device Deselected,
V
IN
≥
V
IH
or V
IN
≤
V
IL
, f = 0
All speed grades
40
mA
Shaded areas contain advance information.
Thermal Resistance
[16]
Parameters
Θ
JA
Description
Test Conditions
Test conditions follow standard
test methods and procedures
for measuring thermal
impedance, per EIA / JESD51.
BGA Typ.
25
fBGA Typ.
27
TQFP Typ.
25
Unit
°C/W
Thermal Resistance
(Junction to Ambient)
Thermal Resistance
(Junction to Case)
Θ
JC
6
6
9
°C/W
Notes:
14.Overshoot: V
IH
(AC) < V
DD
+1.5V (Pulse width less than t
/2), undershoot: V
(AC)> –2V (Pulse width less than t
CYC
/2).
15.T
: Assumes a linear ramp from 0V to V
(min.) within 200 ms. During this time V
IH
< V
DD
and V
DDQ
< V
DD
16.Tested initially and after any design or process changes that may affect these parameters.
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