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參數(shù)資料
| 型號： | CY7C1356CV25-225BGC |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 9-Mbit ( 256K x 36/512K x 18 ) Pipelined SRAM with NoBL-TM Architecture |
| 中文描述： | 9兆位（256 × 36/512K × 18）流水線的SRAM的總線延遲，TM架構(gòu) |
| 文件頁數(shù)： | 17/25頁 |
| 文件大?。?/td> | 353K |
| 代理商： | CY7C1356CV25-225BGC |
PRELIMINARY
CY7C1354CV25
CY7C1356CV25
Document #: 38-05537 Rev. *B
Page 17 of 25
Capacitance
[16]
Parameter
C
IN
C
CLK
C
I/O
Description
Test Conditions
T
A
= 25°C, f = 1 MHz,
V
DD
= 2.5V, V
DDQ
= 2.5V
BGA Max.
5
5
7
fBGA Max.
5
5
7
TQFP Max.
5
5
5
Unit
pF
pF
pF
Input Capacitance
Clock Input Capacitance
Input/Output Capacitance
AC Test Loads and Waveforms
Switching Characteristics
Over the Operating Range
[18, 19]
Parameter
t
Power[17]
Description
-225
-200
-167
Unit
ms
Min.
1
Max.
Min.
1
Max.
Min.
1
Max.
V
CC
(typical) to the First Access Read or
Write
Clock
t
CYC
F
MAX
t
CH
t
CL
Output Times
t
CO
t
EOV
t
DOH
t
CHZ
t
CLZ
t
EOHZ
t
EOLZ
Set-up Times
t
AS
t
DS
t
CENS
t
WES
t
ALS
t
CES
Shaded areas contain advance information.
Notes:
17.This part has a voltage regulator internally; t
power
is the time power needs to be supplied above V
DD
minimum initially, before a Read or Write operation can be
initiated.
18.Timing reference level is when V
= 2.5V.
19.Test conditions shown in (a) of AC Test Loads unless otherwise noted.
20.t
, t
, t
, and t
are specified with AC test conditions shown in (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
21.At any given voltage and temperature, t
is less than t
and t
is less than t
to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
22.This parameter is sampled and not 100% tested.
Clock Cycle Time
Maximum Operating Frequency
Clock HIGH
Clock LOW
4.4
5
6
ns
MHz
ns
ns
225
200
167
1.8
1.8
2.0
2.0
2.4
2.4
Data Output Valid after CLK Rise
OE LOW to Output Valid
Data Output Hold after CLK Rise
Clock to High-Z
[20, 21, 22]
Clock to Low-Z
[20, 21, 22]
OE HIGH to Output High-Z
[20, 21, 22]
OE LOW to Output Low-Z
[20, 21, 22]
2.8
2.8
3.2
3.2
3.5
3.5
ns
ns
ns
ns
ns
ns
ns
1.25
1.25
1.25
1.5
1.5
1.5
1.5
1.5
1.5
2.8
3.2
3.5
2.8
3.2
3.5
0
0
0
Address Set-up before CLK Rise
Data Input Set-up before CLK Rise
1.4
1.4
1.4
1.4
1.4
1.4
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
ns
ns
ns
ns
ns
ns
CEN Set-up before CLK Rise
WE, BW
x
Set-up before CLK Rise
ADV/LD Set-up before CLK Rise
Chip Select Set-up
OUTPUT
R = 1667
R =1538
5 pF
INCLUDING
JIG AND
SCOPE
(a)
(b)
OUTPUT
R
L
= 50
Z
0
= 50
V
T
= 1.25V
2.5V
ALL INPUT PULSES
V
DDQ
GND
90%
10%
90%
10%
≤
1ns
≤
1ns
(c)
2.5V I/O Test Load
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