參數(shù)資料
型號(hào)： CY4615
廠商： Cypress Semiconductor Corp.
英文描述： EZ-USB AT2⑩ USB 2.0 to ATA/ATAPI Bridge
中文描述： 的EZ - USB AT2⑩個(gè)USB 2.0到ATA / ATAPI的橋
文件頁(yè)數(shù)： 9/26頁(yè)
文件大?。?/td> 193K
代理商： CY4615
CY7C68300
Document #: 38-08011 Rev. *B
Page 9 of 26
2.3
Additional Pin Descriptions
2.3.1
DPLUS and DMINUS are the USB signaling pins, and they should be tied to the D+ and D– pins of the USB connector. Because
they operate at high frequencies, the USB signals require special consideration when designing the layout of the PCB.
DPLUS, DMINUS
2.3.2
The clock and data pins for the I
2
C-compatible port should be connected to your configuration EEPROM and to V
CC
through 2.2k
resistors.
SCL, SDA
2.3.3
The EZ-USB AT2 requires a 24-MHz signal to derive internal timing. Typically a 24-MHz parallel-resonant fundamental mode
crystal is used, but a 24-MHz square wave from another source can also be used. If a crystal is used, connect the pins to XTALIN
and XTALOUT, and also through 20-pF capacitors to GND. If an alternate clock source is used, apply it to XTALIN and leave
XTALOUT open.
XTALIN, XTALOUT
Note:
2.
A # sign after the signal name indicates it is an active LOW signal.
36
37
38
39
40
41
42
43
44
45
46
29
30
31
32
33
34
35
36
37
38
39
DIOW#
[2]
DIOR#
DMACK#
V
CC
INTRQ
DA0
DA1
DA2
CS0#
CS1#
VBUS_PW
R_VALID
ARESET#
GND
RESET#
O/Z
[1]
O/Z
[1]
O/Z
[1]
PWR
I
[1]
O/Z
[1]
Driven high after 2 ms delay
O/Z
[1]
Driven high after 2 ms delay
O/Z
[1]
Driven high after 2 ms delay
O/Z
[1]
Driven high after 2 ms delay
O/Z
[1]
Driven high after 2 ms delay
I
Driven high (CMOS)
Driven high (CMOS)
Driven high (CMOS)
ATA Control
.
ATA Control
.
ATA Control
.
V
CC
. Connect to 3.3V power source.
IDE ATA Interrupt request
.
ATA Address
.
ATA Address
.
ATA Address
.
ATA Chip Select
.
ATA Chip Select
.
VBUS detection
. Indicates to the EZ-USB AT2 that VBUS
power is present.
ATA Reset
.
Ground
.
Active LOW Reset
. Resets the entire chip. This pin is
normally tied to VCC through a 100K resistor, and to GND
through a 0.1-μF capacitor, supplying a 10-ms reset.
V
CC
. Connect to 3.3V power source.
Active HIGH
. ATA interface enable. Allows ATA bus sharing
with other host devices. Setting ATA_EN=1 enables the ATA
interface for normal operation. Disabling ATA_EN three-
states (High-Z) the ATA interface and halts the ATA interface
state machine logic.
Input
Input
47
48
49
40
41
42
O/Z
[1]
GND
I
50
51
43
44
V
CC
PWR
I
ATA_EN
Input – If AT2 is not in mfg
mode, polled every 20 ms after
start-up. If LOW, SSOP: pins
36–38, 41–45 and 47 are
three-stated. QFN: pins
29–31, 34–38 and 40 are
three-stated.
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
52
53
54
55
56
45
46
47
48
49
DD8
DD9
DD10
DD11
DD12
I/O
[1]
I/O
[1]
I/O
[1]
I/O
[1]
I/O
[1]
ATA Data bit 8
.
ATA Data bit 9
.
ATA Data bit 10
.
ATA Data bit 11
.
ATA Data bit 12
.
2.2
Pin Descriptions
(continued)
SSOP
Pin
QFN
Pin
Pin Name
Pin
Type
Default State at Start-up
Pin Description
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