參數(shù)資料
型號: CY4615
廠商: Cypress Semiconductor Corp.
英文描述: EZ-USB AT2⑩ USB 2.0 to ATA/ATAPI Bridge
中文描述: 的EZ - USB AT2⑩個USB 2.0到ATA / ATAPI的橋
文件頁數(shù): 10/26頁
文件大?。?/td> 193K
代理商: CY4615
CY7C68300
Document #: 38-08011 Rev. *B
Page 10 of 26
2.3.4
ATA_EN allows bus sharing with other host devices. Setting ATA_EN = 1 enables the ATA interface for normal operation. Setting
ATA_EN = 0 disables (High-Z) the ATA interface pins and removes the EZ-USB AT2 from the USB. The ATA_EN pin is sampled
at a rate of 60 times per second by the EZ-USB AT2 internal logic. This pin should be set to a HIGH at start-up. Upon a HIGH to
LOW transition all EZ-USB AT2 ATA signals are tri-stated, USB is disconnected, and the EZ-USB AT2 enters an idle state until
an active Reset is received, or the ATA_EN pin transitions back to a HIGH state. Upon sensing the LOW to HIGH transition the
EZ-USB AT2 will return to the post Reset operational state, and will reconnect to USB. Note that disabling the ATA bus with the
ATA_EN pin during the middle of a data transfer will result in data loss and can cause the operating system on the Host computer
to crash.
ATA_EN
2.3.5
Design practices as outlined in the ATA/ATAPI-6 Specification for signal integrity should be followed with systems that utilize
a ribbon cable interconnect between the EZ-USB AT2
s ATA interface and the attached ATA/ATAPI device, especially if Ultra DMA
Mode is utilized.
ATA Interface Pins
2.3.6
VBUS_PWR_VALID indicates to the EZ-USB AT2 that power is present on VBUS.
VBUS_PWR_VALID
2.3.7
Asserting RESET# for 10 ms will reset the entire chip. This pin is normally tied to V
CC
through a 100k resistor, and to GND through
a 0.1-
μ
F capacitor.
RESET#
3.0
Applications
The EZ-USB AT2 is a high-speed USB 2.0 peripheral device that connects ATA or ATAPI storage devices to a USB host using
the USB
Mass Storage Class
protocol.
3.1
CY4615 EZ-USB AT2 Reference Design Kit
USB Specification version 2.0
ATA Specification T13/1410D Rev 3B
USB
Mass Storage Class Bulk Only Transport
Specification
, http://www.usb.org/developers/data/devclass/
usbmassbulk_10.pdf.
Additional Resources
Figure 2-4. Typical Reset Circuit
24MHz crystal
20pF
20pF
Figure 2-3. XTALIN, XTALOUT Diagram
C 1
0 . 1 u F d
N R E S E T
R 8
1 0 0 K
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