
CY7C68300
Document #: 38-08011 Rev. *B
Page 3 of 26
LIST OF FIGURES
Figure 1-1. Block Diagram.......................................................................................................................5
Figure 2-1. 56-pin SSOP .........................................................................................................................6
Figure 2-2. 56-pin QFN............................................................................................................................7
Figure 2-3. XTALIN, XTALOUT Diagram...............................................................................................10
Figure 2-4. Typical Reset Circuit ...........................................................................................................10
Figure 11-1. 56-lead Shrunk Small Outline Package 056......................................................................23
Figure 11-2. 56-lead Quad Flatpack No Lead (8 x 8 mm) LF56............................................................23
Figure 13-1. Cross-Section of the Area Underneath the QFN Package................................................24
Figure 13-2. Plot of the Solder Mask (White Area)................................................................................25
Figure 13-3. X-ray Image of the Assembly ............................................................................................25
LIST OF TABLES
Table 5-1. Command Block Wrapper ...................................................................................................11
Table 5-2. Example CfgCB ...................................................................................................................11
Table 5-3. Example MfgCB ...................................................................................................................12
Table 5-4. Mfg_load Data Format .........................................................................................................12
Table 5-5. Mfg_read Data Format ........................................................................................................13
Table 5-6. EEPROM Organization ........................................................................................................14