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| 型號(hào)： | CY4615 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | EZ-USB AT2⑩ USB 2.0 to ATA/ATAPI Bridge |
| 中文描述： | 的EZ - USB AT2⑩個(gè)USB 2.0到ATA / ATAPI的橋 |
| 文件頁(yè)數(shù)： | 8/26頁(yè) |
| 文件大?。?/td> | 193K |
| 代理商： | CY4615 |
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CY7C68300
Document #: 38-08011 Rev. *B
Page 8 of 26
2.2
Pin Descriptions
SSOP
Pin
1
2
3
4
5
6
7
8
9
10
QFN
Pin
50
51
52
53
54
55
56
1
2
3
Pin Name
DD13
DD14
DD15
GND
NC
V
CC
GND
IORDY
DMARQ
AV
CC
Pin
Type
I/O
[1]
I/O
[1]
I/O
[1]
GND
Default State at Start-up
Hi-Z
Hi-Z
Hi-Z
Pin Description
ATA Data bit 13
.
ATA Data bit 14
.
ATA Data bit 15
.
Ground
.
Reserved
. This pin should remain a no-connect.
V
CC
. Connect to 3.3V power source.
Ground
.
ATA Control
.
ATA Control
.
Analog V
CC
. Connect the V
CC
through the shortest path
possible.
24-MHz Crystal Output
(see subsection 2.3.3).
24-MHz Crystal Input
(see subsection 2.3.3).
Analog Ground
. Connect to ground with as short a path as
possible.
V
CC
. Connect to 3.3V power source.
USB D+ Signal
(see subsection 2.3.1).
Hi-Z
PWR
GND
I
[1]
I
[1]
PWR
I
I
11
12
13
4
5
6
XTALOUT
XTALIN
AGND
Xtal
Xtal
GND
Xtal
Xtal
14
15
7
8
V
CC
DPLUS
PWR
I/O
Pulled high at Reset. When
the firmware starts, the pullup
is controlled by pin 46(SSOP)
/ 39(QFN). When VBUS_PWR
_VALID is high, the line is
pulled up. VBUS_PWR
_VALID is polled at start-up
and then every 20 ms.
Hi-Z
16
17
18
19
20
21
22
23
9
DMINUS
GND
V
CC
GND
PU10K
RESERVED
SCL
SDA
I/O
GND
PWR
GND
USB D- Signal
(see subsection 2.3.1).
Ground
.
V
CC
. Connect to 3.3V power source.
Ground
.
Tied to 10k ± 5% pull-up resistor
.
Reserved
. Tie to GND.
Clock signal for I
2
C-compatible interface
(see 2.3.2).
Data signal for I
2
C-compatible interface
(see 2.3.2).
10
11
12
13
14
15
16
Hi-Z
O
I/O
SCL/SDA will be active for
several ms at start-up. Then
driven high.
24
25
26
27
28
29
30
31
32
33
34
35
17
18
19
20
21
22
23
24
25
26
27
28
V
CC
DD0
DD1
DD2
DD3
DD4
DD5
DD6
DD7
GND
V
CC
GND
PWR
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
PWR
GND
V
CC
. Connect to 3.3V power source.
ATA Data bit 0
.
ATA Data bit 1
.
ATA Data bit 2
.
ATA Data bit 3
.
ATA Data bit 4
.
ATA Data bit 5
.
ATA Data bit 6
.
ATA Data bit 7
.
Ground
.
V
CC
. Connect to 3.3V power source.
Ground
.
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Note:
1.
ATA interface pins are not active when ATA_EN is not asserted.
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