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參數(shù)資料
| 型號： | CY28408 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Clock Synthesizer with Differential CPU Outputs |
| 中文描述： | 時鐘合成器的差分輸出的CPU |
| 文件頁數(shù)： | 6/19頁 |
| 文件大?。?/td> | 212K |
| 代理商： | CY28408 |
CY28408
Document #: 38-07617 Rev. **
Page 6 of 19
Spread Spectrum Clock Generation (SSCG)
Spread Spectrum is a modulation technique used to
minimizing EMI reduction generated by repetitive digital
signals. A clock presents the generated EMI energy at the
center frequency it is generating. Spread Spectrum distributes
this energy over a specific and controlled frequency bandwidth
therefore causing the average energy at any point in this band
to decrease in value. This technique is achieved by modulating
the clock away from its resting frequency by a certain
percentage (which also determines the amount of EMI
reduction). In this device, Spread Spectrum is enabled by
setting specific register bits in the SMBus control bytes.
Table 5
is a listing of the modes and percentages of Spread
Spectrum modulation that this device incorporates.
Table 5. Spread Spectrum
Byte 4: 3V66 Control Register
(all bits are read- and write-functional)
Bit
7
6
5
@Pup
0
0
1
Name
Description
SS2 Spread Spectrum control bit (0 = down spread, 1 = center spread)
Reserved
3V66_0 Output Enabled,
1 = enabled, 0 = disabled
3V66_1/VCH Output Enable
1 = enabled, 0 = disabled
3V66_5 Output Enable
1 = enabled, 0 = disabled
3V66_4 Output Enabled
1 = enabled, 0 = disabled
3V66_3 Output Enabled
1 = enabled, 0 = disabled
3V66_2 Output Enabled
1 = enabled, 0 = disabled
3V66_0
4
1
3V66_1/VCH
3
1
3V66_5
2
1
3V66_4
1
1
3V66_3
0
1
3V66_2
Byte 5: Spread Spectrum Control Register
(all bits are read and write functional)
Bit
7
6
5
4
3
2
1
0
@Pup
0
1
0
0
0
0
0
0
Name
Description
SS1 Spread Spectrum control bit
SS0 Spread Spectrum control bit
Reserved
Reserved
Reserved
48M_DOT edge rate control. When set to 1, the edge is slowed by 40%.
Reserved
USB edge rate control. When set to 1, the edge is slowed by 40%.
SS2
0
0
0
0
1
1
1
1
SS1
0
0
1
1
0
0
1
1
SS0
0
1
0
1
0
1
0
1
Spread Mode
Down
Down
Down
Down
Center
Center
Center
Center
Spread%
+0.00, –0.25
+0.00, –0.50
+0.00, –0.75
+0.00, –1.00
+0.13, –0.13
+0.25, –0.25
+0.37, –0.37
+0.50, –1.50
Byte 6: Silicon Signature Register
(all bits are read-only)
Bit
7
6
5
4
3
2
1
0
@Pup
0
0
0
0
1
0
0
0
Name
Description
Revision ID Bit 3
Revision ID Bit 2
Revision ID Bit 1
Revision ID Bit 0
Vendor ID Bit 3
Vendor ID Bit 2
Vendor ID Bit 1
Vendor ID Bit 0
Revision ID Bit 3
Revision ID Bit 2
Revision ID Bit 1
Revision ID Bit 0
Vendor ID Bit 3
Vendor ID Bit 2
Vendor ID Bit 1
Vendor ID Bit 0
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY28408ZC | 制造商:Cypress Semiconductor 功能描述: |
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