參數(shù)資料
型號: CY28408
廠商: Cypress Semiconductor Corp.
英文描述: Clock Synthesizer with Differential CPU Outputs
中文描述: 時鐘合成器的差分輸出的CPU
文件頁數(shù): 15/19頁
文件大?。?/td> 212K
代理商: CY28408
CY28408
Document #: 38-07617 Rev. **
Page 15 of 19
48M_USB
T
DC
T
PERIOD
T
R
/ T
F
T
CCJ
REF
T
DC
T
PERIOD
T
R
/ T
F
T
CCJ
ENABLE/DISABLE and SETUP
T
PZL
/T
PZH
Output Enable Delay (all outputs)
T
PLZ
/T
PHZ
Output Disable Delay (all outputs)
T
STABLE
Clock Stabilization from Power-up
T
SS
Stopclock Setup Time
T
SH
Stopclock Hold Time
Duty Cycle
Period
Rise and Fall Times
Cycle to Cycle Jitter
Measured at 1.5V
Measured at 1.5V
Measured at 0.4 to 2.4V
Measured at 1.5V. See
Table 11
45
55
%
ns
ns
ps
20.8299
1.0
20.8333
2.0
350
REF Duty Cycle
REF Period
REF Rise and Fall Times
REF Cycle to Cycle Jitter
Measured at 1.5V
Measured at 1.5V
Measured at 0.4 to 2.4V
Measured at 1.5V. See
Table 11
45
55
71.0
2.0
1000
%
ns
V/ns
ps
69.84
0.5
1.0
1.0
10.0
0
10.0
10.0
3.0
ns
ns
ms
ns
ns
AC Electrical Specifications
(continued)
Parameter
Description
Condition
Min.
Max.
Unit
Table 11.Maximum Lumped Capacitive Output Loads
Clock
Max Load
30
30
20
10
50
Unit
pF
pF
pF
pF
pF
PCI Clocks
3V66
48M_USB Clock
48M_DOT
REF Clock
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