參數(shù)資料
型號: CY28408
廠商: Cypress Semiconductor Corp.
英文描述: Clock Synthesizer with Differential CPU Outputs
中文描述: 時鐘合成器的差分輸出的CPU
文件頁數(shù): 11/19頁
文件大?。?/td> 212K
代理商: CY28408
CY28408
Document #: 38-07617 Rev. **
Page 11 of 19
PD# – Deassertion
The power-up latency between PD# rising to a valid logic ‘1’
level and the starting of all clocks is less than 1.8 ms.
PCI
PD#
CPUT
CPUC
REF
48M_USB
3V66
Figure 7. Power-down Assertion Timing Waveforms
REF
Tdrive_PWRDN#
<300
μ
s, >200mV
PD#
CPUC
CPUT
3V66
48M_USB
PCI
Tstable
<1.8ms
Figure 8. Power-down Assertion Timing Waveforms
Table 10.PD# Functionality
PD#
1
0
3V66
66 MHz
Low
PCI_F
33 MHz
Low
PCI
USB/DOT
48 MHz
Low
33 MHz
Low
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