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參數(shù)資料
| 型號(hào)： | CY28408 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Clock Synthesizer with Differential CPU Outputs |
| 中文描述： | 時(shí)鐘合成器的差分輸出的CPU |
| 文件頁數(shù)： | 3/19頁 |
| 文件大?。?/td> | 212K |
| 代理商： | CY28408 |
CY28408
Document #: 38-07617 Rev. **
Page 3 of 19
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions, such as individual
clock output buffers, can be individually enabled or disabled.
The registers associated with the Serial Data Interface
initializes to their default setting upon power-up, and therefore
use of this interface is optional. Clock device register changes
are normally made upon system initialization, if any are
required. The interface can also be used during system
operation for power management functions.
Data Protocol
The clock driver serial protocol accepts block write and block
read operations from the controller. For block write/read
operation, the bytes must be accessed in sequential order
from lowest to highest byte (most significant bit first) with the
ability to stop after any complete byte has been transferred.
The block write and block read protocol is outlined in
Table 3
while
Table 4
outlines the corresponding byte write and byte
read protocol. The slave receiver address is 11010010 (D2h).
Table 2. Command Code Definition
Bit
7
(6:0)
Description
0 = Block read or block write operation, 1 = Byte read or byte write operation
Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be
'0000000'
Table 3. Block Read and Block Write Protocol
Block Write Protocol
Description
Block Read Protocol
Description
Bit
1
8:2
9
10
18:11
19
27:20
Bit
1
8:2
9
10
18:11
19
20
Start
Slave address – 7 bits
Write
Acknowledge from slave
Command Code – 8 Bits
Acknowledge from slave
Byte Count – 8 bits
(Skip this step if I
2
C_EN bit set)
Acknowledge from slave
Data byte 1 – 8 bits
Acknowledge from slave
Data byte 2 – 8 bits
Acknowledge from slave
Data Byte /Slave Acknowledges
Data Byte N –8 bits
Acknowledge from slave
Stop
Start
Slave address – 7 bits
Write
Acknowledge from slave
Command Code – 8 Bits
Acknowledge from slave
Repeat start
28
27:21
28
29
37:30
38
46:39
47
55:48
56
....
....
....
...
Slave address – 7 bits
Read = 1
Acknowledge from slave
Byte Count from slave – 8 bits
Acknowledge
Data byte 1 from slave – 8 bits
Acknowledge
Data byte 2 from slave – 8 bits
Acknowledge
Data bytes from slave / Acknowledge
Data Bte N from slave – 8 bits
NOT Acknowledge
Stop
36:29
37
45:38
46
....
....
....
....
Table 4. Byte Read and Byte Write Protocol
Byte Write Protocol
Description
Byte Read Protocol
Description
Bit
1
8:2
9
10
18:11
Bit
1
8:2
9
10
18:11
Start
Slave address – 7 bits
Write
Acknowledge from slave
Command Code – 8 bits
Start
Slave address – 7 bits
Write
Acknowledge from slave
Command Code – 8 bits
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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