參數(shù)資料
型號: CY22E016L
廠商: Cypress Semiconductor Corp.
英文描述: 16-Kbit (2K x 8) nvSRAM
中文描述: 16千位(2K × 8)非易失
文件頁數(shù): 9/14頁
文件大小: 748K
代理商: CY22E016L
PRELIMINARY
CY22E016L
Document #: 001-06727 Rev. *C
Page 9 of 14
Hardware STORE Cycle
Parameter
t
STORE [6]
t
DELAY [10]
t
RESTORE [11]
t
HLHX
t
HLBL
Description
CY22E016L
Min
Unit
ms
μ
s
ns
ns
ns
Max
10
STORE Cycle Duration
Time allowed to complete SRAM Cycle
Hardware STORE High to Inhibit Off
Hardware STORE Pulse Width
Hardware STORE Low to STORE Busy
1
700
15
300
Switching Waveforms
Figure 6. SRAM Read Cycle #1: Address Controlled
[4, 5, 12]
Figure 7. SRAM Read Cycle #2: CE Controlled
[4,12]
Notes:
10.Read and Write cycles in progress before HSB are given this amount of time to complete.
11. t
is only applicable after t
is complete.
12.HSB must remain HIGH during READ and WRITE cycles.
t
RC
t
AA
t
OH
ADDRESS
DQ (DATA OUT)
DATA VALID
ADDRESS
t
RC
CE
t
ACE
t
LZCE
t
PD
t
HZCE
OE
t
DOE
t
LZOE
t
HZOE
DATA VALID
ACTIVE
STANDBY
t
PU
DQ (DATA OUT)
ICC
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