參數(shù)資料
型號: CY22E016L-SZ35XCT
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: DRAM
英文描述: 16-Kbit (2K x 8) nvSRAM
中文描述: 2K X 8 NON-VOLATILE SRAM, 35 ns, PDSO28
封裝: 0.300 INCH, ROHS COMPLIANT, MO-119, SOIC-28
文件頁數(shù): 1/14頁
文件大?。?/td> 748K
代理商: CY22E016L-SZ35XCT
PRELIMINARY
16-Kbit (2K x 8) nvSRAM
CY22E016L
Cypress Semiconductor Corporation
Document #: 001-06727 Rev. *C
198 Champion Court
San Jose
,
CA 95134-1709
408-943-2600
Revised November 28, 2006
Features
25 ns, 35 ns and 45 ns Access Times
“Hands-off” Automatic
STORE
on Power Down with
external 68
μ
F
capacitor
STORE
to QuantumTrap
Nonvolatile Elements is
initiated by Hardware or Autostore
on Power-down
RECALL
to SRAM Initiated on Power-up
Infinite
READ, WRITE
and
RECALL
Cycles
10 mA Typical I
CC
at 200 ns Cycle Time
1,000,000
STORE
Cycles to QuantumTrap
100-Year Data Retention to QuantumTrap
Single 5V Operation +10%
Commercial, Industrial Temperature
SOIC Package
RoHS Compliance
Functional Description
The Cypress CY22E016L is a fast static RAM
with a nonvol-
atile element incorporated in each static memory cell. The
SRAM
can be read and written an infinite number of times,
while independent, nonvolatile data resides in Nonvolatile
Elements. Data transfers from the SRAM
to the Nonvolatile
Elements (the STORE
operation) can take place automatically
on power down. A 68-
μ
F or larger capacitor tied from V
CAP
to
ground guarantees the STORE
operation, regardless of
power-down slew rate or loss of power from “hot swapping”.
Transfers from the Nonvolatile Elements to the SRAM
(the
RECALL
operation) take place automatically on restoration of
power. A hardware STORE
may be initiated with the HSB pin.
Logic Block Diagram
STORE/
RECALL
CONTROL
POWER
CONTROL
STATIC RAM
ARRAY
32 X 512
Quantum Trap
32 X 512
STORE
RECALL
COLUMN I/O
COLUMN DEC
R
I
OE
CE
WE
HSB
V
CC
V
CAP
A
0
A
1
A
2
A
3
A
4
A
10
A
5
A
6
A
7
A
8
A
9
DQ
0
DQ
1
DQ
2
DQ
3
DQ
4
DQ
5
DQ
6
DQ
7
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