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參數(shù)資料
| 型號： | CY22E016L |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 16-Kbit (2K x 8) nvSRAM |
| 中文描述： | 16千位（2K × 8）非易失 |
| 文件頁數(shù)： | 3/14頁 |
| 文件大?。?/td> | 748K |
| 代理商： | CY22E016L |
PRELIMINARY
CY22E016L
Document #: 001-06727 Rev. *C
Page 3 of 14
Device Operation
The CY22E016L nvSRAM is made up of two functional
components paired in the same physical cell. These are a
SRAM memory cell and a nonvolatile QuantumTrap cell. The
SRAM memory cell operates as a standard fast static RAM.
Data in the SRAM can be transferred to the nonvolatile cell
(the STORE operation), or from the nonvolatile cell to SRAM
(the RECALL operation). This unique architecture allows all
cells to be stored and recalled in parallel. During the STORE
and RECALL operations SRAM READ and WRITE operations
are inhibited. The CY22E016L supports infinite reads and
writes just like a typical SRAM. In addition, it provides infinite
RECALL operations from the nonvolatile cells and up to
1 million STORE operations.
SRAM Read
The CY22E016L performs a READ cycle whenever CE and
OE are low while WE and HSB are high. The address specified
on pins A
0–10
determines which of the 2,048 data bytes will be
accessed. When the READ is initiated by an address
transition, the outputs will be valid after a delay of t
AA
(READ
cycle #1). If the READ is initiated by CE or OE, the outputs will
be valid at t
ACE
or at t
DOE
, whichever is later (READ cycle #2).
The data outputs will repeatedly respond to address changes
within the t
AA
access time without the need for transitions on
any control input pins, and will remain valid until another
address change or until CE or OE is brought high, or WE or
HSB is brought low.
SRAM Write
A WRITE cycle is performed whenever CE and WE are low
and HSB is high. The address inputs must be stable prior to
entering the WRITE cycle and must remain stable until either
CE or WE goes high at the end of the cycle. The data on the
common I/O pins I/O
0–7
will be written into the memory if it is
valid t
SD
before the end of a WE controlled WRITE or before
the end of an CE controlled WRITE. It is recommended that
OE be kept high during the entire WRITE cycle to avoid data
bus contention on common I/O lines. If OE is left low, internal
circuitry will turn off the output buffers t
HZWE
after WE goes
low.
AutoStore Operation
During normal AutoStore operation, the CY22E016L will draw
current from V
CC
to charge a capacitor connected to the V
CAP
pin. This stored charge will be used by the chip to perform a
single STORE
operation. After power up, when the voltage on
the V
CAP
pin drops below V
SWITCH
, the part will automatically
disconnect the V
CAP
pin from V
CC
and initiate a STORE
operation.
Figure 1
shows the proper connection of the storage capacitor
(V
CAP
) for automatic store operation. A charge storage
capacitor having a capacity of between 68
μ
F and 220
μ
F
(±20%) rated at 6V should be provided.In system power mode
both V
CC
and V
CAP
are connected to the +5V power supply
without the 68-
μ
F capacitor. In this mode the AutoStore
function of the CY22E016L will operate on the stored system
charge as power goes down. The user must, however,
guarantee that V
CC
does not drop below 3.6V during the
If an automatic STORE
on power loss is not required, then V
CC
can be tied to ground and +5V applied to V
CAP
. This is the
AutoStore Inhibit mode, in which the AutoStore function is
disabled. If the CY22E016L is operated in this configuration,
references to V
CC
should be changed to V
CAP
throughout this
data sheet. In this mode, STORE
operations may be triggered
with the HSB pin. It is not permissible to change between these
three options “on the fly”.
Figure 1. AutoStore
Mode
Figure 2. System Power Mode
28
1
1
6
U
6
1
27
26
14
15
0
U
B
28
1
1
1
27
26
14
15
0
U
B
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