參數(shù)資料
型號: CY22E016L
廠商: Cypress Semiconductor Corp.
英文描述: 16-Kbit (2K x 8) nvSRAM
中文描述: 16千位(2K × 8)非易失
文件頁數(shù): 2/14頁
文件大?。?/td> 748K
代理商: CY22E016L
PRELIMINARY
CY22E016L
Document #: 001-06727 Rev. *C
Page 2 of 14
Pin Configurations
Pin Definitions
Pin Name
A
0
–A
10
DQ0-DQ7
I/O Type
Input
Input/Output
Bidirectional Data I/O lines
. Used as input or output lines depending on operation.
Input
Write Enable Input, active LOW
. When selected LOW, enables data on the I/O pins to be written to
the address location latched by the falling edge of CE.
Input
Chip Enable Input, active LOW
. When LOW, selects the chip. When HIGH, deselects the chip.
Input
Output Enable, active LOW
. The active LOW OE input enables the data output buffers during read
cycles. Deasserting OE HIGH causes the I/O pins to tri-state.
Ground
Ground for the device
.
Should be connected to ground of the system.
Power Supply
Power Supply inputs to the device
.
Input/Output
Hardware Store Busy
. When low this output indicates a Hardware Store is in progress. When pulled
low external to the chip it will initiate a nonvolatile STORE operation. A weak internal pull-up resistor
keeps this pin high if not connected. (Connection Optional)
Power Supply
Autostore
Capacitor
. Supplies power to nvSRAM during power loss to store data from SRAM to
nonvolatile elements.
No Connect
No Connects.
This pin is not connected to the die
Description
Address Inputs used to select one of the 2,048
bytes of the nvSRAM
.
WE
CE
OE
V
SS
V
CC
HSB
V
CAP
NC
V
CAP
A
7
A
6
A
5
A
4
V
CC
HSB
WE
A
8
A
9
OE
A
10
DQ6
DQ7
DQ5
CE
DQ4
DQ3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
V
SS
DQ0
A
3
A
2
A
1
A
0
DQ1
DQ2
28-SOIC
Top View
(Not To Scale)
NC
NC
28
27
26
25
24
23
22
21
20
19
18
17
16
15
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