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參數(shù)資料
| 型號： | CXA3266Q |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PHASE LOCKED LOOP, 0.12 MHz, PQFP48 |
| 封裝： | PLASTIC, QFP-48 |
| 文件頁數(shù)： | 53/62頁 |
| 文件大?。?/td> | 929K |
| 代理商： | CXA3266Q |
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CXA3266Q
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Power
SCAN :
This is the control register read setting. When this is ON, the control register serial
data is output from SEROUT (Pin 15). This should normally be set to OFF.
SYNTH :
This is the enable/disable setting for this IC. This should normally be set to ON.
VCO By-pass : This is set to OFF when testing the program counter. This should normally be set to ON.
O/P Enable
These are the enable/disable settings for each TTL output (DIVOUT, UNLOCK, DSYNC, CLK2,
NCLK2, CLK1 and NCLK1). Set to ON when performing evaluation using TTL output.
DSYNC Functions
DELAY :
When DIVOUT is output from DSYNC output, its delay is set. 4CLK for OFF ; 5CLK
for ON.
WIDTH :
When DIVOUT is output from DSYNC output, its pulse width is changed. Their settings
are 1CLK for “00”, 2CLK for “01”, 4CLK for “10”, and 8CLK for “11”.
HOLD :
DSYNC output status is set during HOLD. Output OFF status for OFF (H or L fixed
according to DSYNC POL polarity) ; DSYNC or DIVOUT are output for ON.
BYPASS :
DSYNC/DIVOUT output switching from DSYNC output is performed.
DSYNC is output for ON ; DIVOUT for OFF.
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