參數(shù)資料
型號(hào)： CXA3266Q
元件分類： PLL合成/DDS/VCOs
英文描述： PHASE LOCKED LOOP, 0.12 MHz, PQFP48
封裝： PLASTIC, QFP-48
文件頁數(shù)： 26/62頁
文件大?。?/td> 929K
代理商： CXA3266Q
CXA3266Q
- 32 -
Relationship between SYNC Input and DSYNC Output during HOLD
When the above SYNC internal and DIVOUTN internal signals are input, the DSYNC internal signal is output
as shown in the table below.
1. DSYNC = L when SYNC = L and DIVOUTN = L.
2. DSYNC = H* or L* (unchanged with the previous data) when SYNC = H and DIVOUTN = L.
3. DSYNC = H when DIVOUTN = H (SYNC = H or L)
( * ) is unchanged with the previous data.
SYNC
DIVOUTN
J
K
Q
DSYNC
LL
H*
L*
(1)
HLHL
L
(2)
LHLHL
H
(3)
HL
LL
L*
H*
(4)
LL
H*
L*
(5)
HH
L
H
L
H
(6)
J
K
Q
CK
CLK
DSYNC
internal signal
SYNC
internal signal
DIVOUTN
internal signal
SYNC
internal signal
DIVOUTN
DSYNC
(1)
(5)
(6)
(4)
(2)
(3)
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