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參數(shù)資料
| 型號： | CXK77P18L80AGB-4A |
| 元件分類： | SRAM |
| 英文描述： | 512K X 18 LATE-WRITE SRAM, 3.8 ns, PBGA119 |
| 封裝： | 14 X 22 MM, 1.27 MM PITCH, PLASTIC, BGA-119 |
| 文件頁數(shù)： | 1/25頁 |
| 文件大?。?/td> | 269K |
| 代理商： | CXK77P18L80AGB-4A |
8Mb LW R-L, rev 1.1
1 / 25
May 22, 2002
CXK77P36L80AGB / CXK77P18L80AGB
SONY
4/42/43/44
8Mb LW R-L HSTL High Speed Synchronous SRAMs (256K x 36 or 512K x18)
Preliminary
Description
Features
4 Speed Bins
Cycle Time / Access Time
-4
(-4A) (-4B)
4.0ns / 3.9ns (3.8ns) (3.7ns)
-42 (-42A) (-42B)
4.2ns / 4.2ns (4.1ns) (4.0ns)
-43 (-43A) (-43B)
4.3ns / 4.5ns (4.4ns) (4.3ns)
-44
4.4ns / 4.7ns
Single 3.3V power supply (VDD): 3.3V ± 5%
Dedicated output supply voltage (VDDQ): 1.5V typical
Extended HSTL-compatible I/O interface with dedicated input reference voltage (VREF): 0.75V typical
Register - Latch (R-L) read operations
Late Write (LW) write operations
Full read/write coherency
Byte Write capability
Differential input clocks (K/K)
Asynchronous output enable (G)
Programmable impedance output drivers
Sleep (power down) mode via dedicated mode pin (ZZ)
JTAG boundary scan (subset of IEEE standard 1149.1)
119 pin (7x17), 1.27mm pitch, 14mm x 22mm Ball Grid Array (BGA) package
The CXK77P36L80AGB (organized as 262,144 words by 36 bits) and the CXK77P18L80AGB (organized as 524,288 words
by 18 bits) are high speed CMOS synchronous static RAMs with common I/O pins. These synchronous SRAMs integrate input
registers, high speed RAM, output latches, and a one-deep write buffer onto a single monolithic IC. Register - Latch (R-L) read
operations and Late Write (LW) write operations are supported, providing a high-performance user interface.
All address and control input signals except G (Output Enable) and ZZ (Sleep Mode) are registered on the rising edge of K
(Input Clock).
During read operations, output data is driven valid from the falling edge of K, one half clock cycle after the address is registered.
During write operations, input data is registered on the rising edge of K, one full clock cycle after the address is registered.
The output drivers are series terminated, and the output impedance is programmable through an external impedance matching
resistor RQ. By connecting RQ between ZQ and VSS, the output impedance of all DQ pins can be precisely controlled.
Sleep (power down) mode control is provided through the asynchronous ZZ input. 250 MHz operation is obtained from a single
3.3V power supply. JTAG boundary scan interface is provided using a subset of IEEE standard 1149.1 protocol.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CXK77P18R160GB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MEMORY-UHS Synch SRAMs＜/A＞＜/I＞ 16Meg Ultra-High-Speed Synchronous SRAM (1M x 18) (22 pages 233K Rev. 6/3/02) |
| CXK77P36E160GB | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:16Mb LW R-L HSTL High Speed Synchronous SRAMs (512K x 36 or 1M x 18) |
| CXK77P36E160GB-42AE | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:16Mb LW R-L HSTL High Speed Synchronous SRAMs (512K x 36 or 1M x 18) |
| CXK77P36E160GB-42BE | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:16Mb LW R-L HSTL High Speed Synchronous SRAMs (512K x 36 or 1M x 18) |
| CXK77P36E160GB-42E | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:16Mb LW R-L HSTL High Speed Synchronous SRAMs (512K x 36 or 1M x 18) |
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