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參數(shù)資料
| 型號： | CXK77P18L80AGB-4A |
| 元件分類： | SRAM |
| 英文描述： | 512K X 18 LATE-WRITE SRAM, 3.8 ns, PBGA119 |
| 封裝： | 14 X 22 MM, 1.27 MM PITCH, PLASTIC, BGA-119 |
| 文件頁數(shù)： | 13/25頁 |
| 文件大小： | 269K |
| 代理商： | CXK77P18L80AGB-4A |
SONY
CXK77P36L80AGB / CXK77P18L80AGB
Preliminary
8Mb LW R-L, rev 1.1
20 / 25
May 22, 2002
TAP Instructions
IDCODE
IDCODE is the default instruction loaded into the Instruction Register at power-up, and when the TAP Controller is in the
“Test-Logic Reset” state.
When the IDCODE instruction is selected, a predetermined device- and manufacturer-specific identification code is load-
ed into the ID Register when the TAP Controller is in the “Capture-DR” state, and the ID Register is inserted between
TDI and TDO when the TAP Controller is in the “Shift-DR” state.
Normal SRAM operation is not disrupted when the IDCODE instruction is selected.
BYPASS
When the BYPASS instruction is selected, a logic “0” is loaded into the Bypass Register when the TAP Controller is in
the “Capture-DR” state, and the Bypass Register is inserted between TDI and TDO when the TAP Controller is in the
“Shift-DR” state.
Normal SRAM operation is not disrupted when the BYPASS instruction is selected.
SAMPLE
When the SAMPLE instruction is selected, the individual logic states of all signals composing the SRAM’s I/O ring (see
the Boundary Scan Register description for the complete list of signals) are loaded into the Boundary Scan Register when
the TAP Controller is in the “Capture-DR” state, and the Boundary Scan Register is inserted between TDI and TDO when
the TAP Controller is in the “Shift-DR” state.
Normal SRAM operation is not disrupted when the SAMPLE instruction is selected.
SAMPLE-Z
When the SAMPLE-Z instruction is selected, the individual logic states of all signals composing the SRAM’s I/O ring
(see the Boundary Scan Register description for the complete list of signals) are loaded into the Boundary Scan Register
when the TAP Controller is in the “Capture-DR” state, and the Boundary Scan Register is inserted between TDI and TDO
when the TAP Controller is in the “Shift-DR” state.
Additionally, when the SAMPLE-Z instruction is selected, the SRAM’s data output drivers are disabled (that is, the DQ
I/O buffers are forced to an input state).
Consequently, normal SRAM operation is disrupted when the SAMPLE-Z instruction is selected. Read operations initi-
ated while the SAMPLE-Z instruction is selected will fail.
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參數(shù)描述 |
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| CXK77P18R160GB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MEMORY-UHS Synch SRAMs＜/A＞＜/I＞ 16Meg Ultra-High-Speed Synchronous SRAM (1M x 18) (22 pages 233K Rev. 6/3/02) |
| CXK77P36E160GB | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:16Mb LW R-L HSTL High Speed Synchronous SRAMs (512K x 36 or 1M x 18) |
| CXK77P36E160GB-42AE | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:16Mb LW R-L HSTL High Speed Synchronous SRAMs (512K x 36 or 1M x 18) |
| CXK77P36E160GB-42BE | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:16Mb LW R-L HSTL High Speed Synchronous SRAMs (512K x 36 or 1M x 18) |
| CXK77P36E160GB-42E | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:16Mb LW R-L HSTL High Speed Synchronous SRAMs (512K x 36 or 1M x 18) |
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