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參數(shù)資料
| 型號： | CXK77P18L80AGB-4A |
| 元件分類： | SRAM |
| 英文描述： | 512K X 18 LATE-WRITE SRAM, 3.8 ns, PBGA119 |
| 封裝： | 14 X 22 MM, 1.27 MM PITCH, PLASTIC, BGA-119 |
| 文件頁數(shù)： | 21/25頁 |
| 文件大?。?/td> | 269K |
| 代理商： | CXK77P18L80AGB-4A |
SONY
CXK77P36L80AGB / CXK77P18L80AGB
Preliminary
8Mb LW R-L, rev 1.1
5 / 25
May 22, 2002
Clock Truth Table
Sleep (Power Down) Mode
Sleep (power down) mode is provided through the asynchronous input signal ZZ. When ZZ is asserted (high), the output
drivers will go to a Hi-Z state, and the SRAM will begin to draw standby current. Contents of the memory array will be
preserved. An enable time (tZZE) must be met before the SRAM is guaranteed to be in sleep mode, and a recovery time
(tZZR) must be met before the SRAM can resume normal operation.
Programmable Impedance Output Drivers
These devices have programmable impedance output drivers. The output impedance is controlled by an external resistor
RQ connected between the SRAM’s ZQ pin and VSS, and is equal to one-fifth the value of this resistor, nominally. See
the DC Electrical Characteristics section for further information.
Output Driver Impedance Power-Up Requirements
Output driver impedance will reach the programmed value within 8192 cycles after power-up. Consequently, it is recom-
mended that Read operations not be initiated until after the initial 8192 cycles have elapsed.
Output Driver Impedance Updates
Output driver impedance is updated during Write and Deselect operations when the output driver is disabled.
Power-Up Sequence
For reliability purposes, Sony recommends that power supplies power up in the following sequence: VSS, VDD, VDDQ,
VREF, and Inputs. VDDQ should never exceed VDD. If this power supply sequence cannot be met, a large bypass diode
may be required between VDD and VDDQ. Please contact Sony Memory Application Department for further information.
K
ZZ
SS
(tn)
SW
(tn)
SBWx
(tn)
G
Operation
DQ
(tn)
DQ
(tn+1)
X
H
X
Sleep (Power Down) Mode
Hi - Z
L
→H
L
H
X
Deselect
Hi - Z
X
L
→H
L
H
X
H
Read
Hi - Z
L
→H
L
H
X
L
Read
Q(tn)
X
L
→H
L
X
Write All Data Bytes
Hi - Z
D(tn)
L
→H
L
X
Write Data Byte x if SBWx = L
Hi - Z
D(tn)
L
→H
L
H
X
Abort Write
Hi - Z
X
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CXK77P18R160GB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MEMORY-UHS Synch SRAMs＜/A＞＜/I＞ 16Meg Ultra-High-Speed Synchronous SRAM (1M x 18) (22 pages 233K Rev. 6/3/02) |
| CXK77P36E160GB | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:16Mb LW R-L HSTL High Speed Synchronous SRAMs (512K x 36 or 1M x 18) |
| CXK77P36E160GB-42AE | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:16Mb LW R-L HSTL High Speed Synchronous SRAMs (512K x 36 or 1M x 18) |
| CXK77P36E160GB-42BE | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:16Mb LW R-L HSTL High Speed Synchronous SRAMs (512K x 36 or 1M x 18) |
| CXK77P36E160GB-42E | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:16Mb LW R-L HSTL High Speed Synchronous SRAMs (512K x 36 or 1M x 18) |
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