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參數(shù)資料
| 型號(hào)： | CXK77P18L80AGB-4A |
| 元件分類： | SRAM |
| 英文描述： | 512K X 18 LATE-WRITE SRAM, 3.8 ns, PBGA119 |
| 封裝： | 14 X 22 MM, 1.27 MM PITCH, PLASTIC, BGA-119 |
| 文件頁數(shù)： | 14/25頁 |
| 文件大小： | 269K |
| 代理商： | CXK77P18L80AGB-4A |
SONY
CXK77P36L80AGB / CXK77P18L80AGB
Preliminary
8Mb LW R-L, rev 1.1
21 / 25
May 22, 2002
TAP Controller
The TAP Controller is a 16-state state machine that controls access to the various TAP Registers and executes the opera-
tions associated with each TAP Instruction. State transitions are controlled by TMS and occur on the rising edge of TCK.
The TAP Controller enters the “Test-Logic Reset” state in one of two ways:
1. At power up.
2. When a logic “1” is applied to TMS for at least 5 consecutive rising edges of TCK.
The TDI input receiver is sampled only when the TAP Controller is in either the “Shift-IR” state or the “Shift-DR” state.
The TDO output driver is active only when the TAP Controller is in either the “Shift-IR” state or the “Shift-DR” state.
TAP Controller State Diagram
Figure 7
Test-Logic Reset
Run-Test / Idle
Select DR-Scan
Select IR-Scan
Capture-DR
Capture-IR
Shift-DR
Shift-IR
Exit1-DR
Exit1-IR
Pause-DR
Pause-IR
Exit2-DR
Exit2-IR
Update-DR
Update-IR
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
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| CXK77P18R160GB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MEMORY-UHS Synch SRAMs＜/A＞＜/I＞ 16Meg Ultra-High-Speed Synchronous SRAM (1M x 18) (22 pages 233K Rev. 6/3/02) |
| CXK77P36E160GB | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:16Mb LW R-L HSTL High Speed Synchronous SRAMs (512K x 36 or 1M x 18) |
| CXK77P36E160GB-42AE | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:16Mb LW R-L HSTL High Speed Synchronous SRAMs (512K x 36 or 1M x 18) |
| CXK77P36E160GB-42BE | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:16Mb LW R-L HSTL High Speed Synchronous SRAMs (512K x 36 or 1M x 18) |
| CXK77P36E160GB-42E | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:16Mb LW R-L HSTL High Speed Synchronous SRAMs (512K x 36 or 1M x 18) |
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