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參數(shù)資料
| 型號： | CXA3266Q |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PHASE LOCKED LOOP, 0.12 MHz, PQFP48 |
| 封裝： | PLASTIC, QFP-48 |
| 文件頁數(shù)： | 49/62頁 |
| 文件大?。?/td> | 929K |
| 代理商： | CXA3266Q |
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CXA3266Q
- 53 -
Setting Methods and Notes on Operation
Input Pins
This PWB supports TTL single and PECL complementary input.
Input pins : SYNC : TTL level input, 10 to 120kHz
SYNCL : PECL Low level input, 10 to 120kHz
SYNCH : PECL High level input, 10 to 120kHz
VCO :
TTL level input. This is a test pin and is therefore normally not used.
VCOL : PECL Low level input. This is a test pin and is therefore normally not used.
VCOH : PECL High level input. This is a test pin and is therefore normally not used.
Output Pins
This PWB supports TTL single and PECL complementary output.
DSYNCH, DSYNCL : PECL level complementary delay SYNC outputs. The output range is 10 to 120kHz.
DSYNC :
TTL level delay SYNC output. The output range is 10 to 120kHz.
CLKH, CLKL :
PECL level complementary CLK outputs. The output range is 5 to 203MHz.
CLK, CLKN :
TTL level complementary CLK outputs. The output range is 5 to 100MHz.
CLK/2H, CLK/2L :
PECL level complementary 1/2 CLK outputs. The output range is 2.5 to 100MHz.
CLK/2, CLK/2N :
TTL level complementary CLK outputs. The output range is 2.5 to 100MHz.
VBB :
Outputs the PECL amplitude threshold voltage.
SEROUT :
TTL level control register serial data output.
DIVOUT :
TTL level internal programmable counter test output.
UNLOCK :
TTL level UNLOCK output. This pin requires external circuits such as appropriate
capacitors and resistors.
See the IC specifications for a detailed description.
PECL outputs (VBB, DSYNCH, DSYNCL, CLKH, CLKL, CLK/2H, CLK/2L) are output constantly, but TTL
outputs (DSYNC, CLK, CLKN, CLK/2, CLK/2N, SEROUT, DIVOUT, UNLOCK) are controlled by the respective
control registers. Therefore, the enable/disable settings should be made in accordance with the application.
See the following pages for the setting method.
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