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參數(shù)資料
| 型號(hào)： | CXA3266Q |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PHASE LOCKED LOOP, 0.12 MHz, PQFP48 |
| 封裝： | PLASTIC, QFP-48 |
| 文件頁數(shù)： | 36/62頁 |
| 文件大?。?/td> | 929K |
| 代理商： | CXA3266Q |
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CXA3266Q
- 41 -
CLK Jitter Evaluation Method
The regenerated CLK is obtained by applying Hsync to the CXA3266Q. Apply this CLK to a digital oscilloscope
and observe the CLK waveform using Hsync as the trigger.
The CLK jitter is measured at peak to peak in the long-term write mode of the digital oscilloscope as shown in
the figure. The CLK jitter size varies according to the difference in the relative position with respect to Hsync.
Therefore, when the observation point is changed, the CLK jitter at that point is observed.
The figure below shows a typical example of the CLK jitter for the CXA3266Q.
The CLK jitter increases slightly at the rising edge of Hsync (in the case of positive polarity), and then settles
down thereafter. However, this is not a problem as the active pixels start after about 20% of the H cycle has
passed from the rising edge of Hsync.
Digital
Oscillo
Scope
CXA3266Q
trigger
Pulse
Generator
ch1
CLK
Hsync
H
Sync
Back
Porch
Front
Porch
Active
Video
15 to 25% of Tsync
Tsync = 1/fsync
Enlarged
CLK
Tjp-p
Trigger
CLK
Hsync
Computer signal
0
1/4 Tsync
2/4 Tsync
3/4 Tsync
Tsync
Observation points
Jitter
amount
[Tjp-p]
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