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參數(shù)資料
| 型號： | CXA3266Q |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PHASE LOCKED LOOP, 0.12 MHz, PQFP48 |
| 封裝： | PLASTIC, QFP-48 |
| 文件頁數(shù)： | 2/62頁 |
| 文件大小： | 929K |
| 代理商： | CXA3266Q |
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CXA3266Q
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15 SEROUT OTTL
Register read output.
When SENABLE is High, the register
contents are output from SEROUT at
the falling edge of SCLK.
(See the Control Register Timing
Chart.)
TTL output can be turned ON/OFF
(high impedance) by a control
register.
16 DIVOUT
O
TTL
Programmable counter test output.
(See the I/O Timing Chart.)
TTL output can be turned ON/OFF
(high impedance) by a control
register.
20 CLK/2N
O
TTL
Inverted 1/2 clock output.
(See the I/O Timing Chart.)
TTL output can be turned ON/OFF
(high impedance) by a control
register.
21 CLK/2O
TTL
1/2 clock output.
(See the I/O Timing Chart.)
TTL output can be turned ON/OFF
(high impedance) by a control
register.
22 CLKN
O
TTL
Inverted clock output.
(See the I/O Timing Chart.)
TTL output can be turned ON/OFF
(high impedance) by a control
register.
23 CLK
O
TTL
Clock output.
(See the I/O Timing Chart.)
TTL output can be turned ON/OFF
(high impedance) by a control
register.
24 DSYNC
O
TTL
Delay sync signal output.
(See the I/O Timing Chart.)
TTL output can be turned ON/OFF
(high impedance) and switched
between positive/negative polarity
by a control register.
17 UNLOCK OTTL
Unlock signal output.
This pin is an open collector output,
and pulls in the current when a
phase difference occurs. The
UNLOCK sensitivity can be adjusted
by connecting a capacitor and
resistors to this output appropriately.
(See the UNLOCK Timing Chart.)
TTL output can be turned ON/OFF
(high impedance) by a control register.
Pin
No.
Symbol I/O
Reference
voltage level
Equivalent circuit
Description
IOVCC
IOGND
TTLVCC
TTLGND
100k
15
16
20
21
22
23
24
TTLVCC
IOGND
TTLGND
17
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