參數(shù)資料
型號: BGB110
廠商: NXP SEMICONDUCTORS
元件分類: 通信及網(wǎng)絡(luò)
英文描述: Bluetooth radio module
中文描述: SPECIALTY TELECOM CIRCUIT, XMA34
封裝: 13.75 X 10.20 X 1.90 MM, LEADLESS, METAL CAP, SOT, MODULE-34
文件頁數(shù): 9/17頁
文件大?。?/td> 141K
代理商: BGB110
2000 Oct 03
9
Philips Semiconductors
Objective specification
Bluetooth radio module
BGB110
GFSK_TABLE
The GFSK_TABLE register defines the Gaussian filtering of the datastream to be transmitted. It consists of 13 registers,
the contents of which define the shape of the Gaussian-filtered modulating signal. There is an auto-increment facility, so
that subsequent writes to this register result in subsequent shape values being written. Setting the
grst
bit in the
ENABLE register to
1
resets the auto-increment counter. It should be reset to
0
before loading the shape values.
The values into this table depend on the supply voltage. Below is given an example table that can be used for a 3.0 V
supply voltage. If there is a different supply voltage, these values should be scaled accordingly.
Reset
The BGB110 has an internal power-on reset function, which is operational every time the supply voltage is switched on.
This will reset all internal registers and will bring the device into a known state. Next to the built-in power-on reset, there
is the POR_EXT reset signal. This will also reset the device and put it into the same state as the power-on reset. The
POR_EXT signal is intended to be used as a reset from a host processor.
Following the power-on reset or a POR_EXT reset, the system oscillator is started and the SYS_CLK output is activated
(enabled). The SYS_CLK can be controlled by the SYS_CLK_REQ signal. It will only control the SYS_CLK once the Rdy
bit in the CONTROL register has been set. The function of the SYS_CLK _REQ has two phases:
1.
After reset, the SYS_CLK_REQ is not taken into account for generation of SYS_CLK. The 13 MHz system clock is
enabled on SYS_CLK.
2.
Once register CONTROL Rdy is set to
1
, the 13 MHz system clock on the SYS_CLK is controlled by
SYS_CLK_REQ.
SYS_CLK_REQ does not control the oscillator itself. The oscillator will not be disabled by the SYS_CLK_REQ signal.
LPO_CLK output is only controlled by the POR_EXT which also controls the POR output. POR is activated 4 SYS_CLK
cycles after POR_EXT.
GFSK_TABLE
b7
b6
b5
b4
b3
b2
b1
b0
28
GFSK_TABLE
Bits b7 -b0
GFSK_TABLE
Gaussian filter shape value
Shape value #
0
1
2
3
4
5
6
7
8
9
10
11
12
Value
0x3B
0x3C
0x3E
0x42
0x4A
0x57
0x66
0x75
0x82
0x8A
0x8E
0x90
0x91
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