2000 Oct 03
5
Philips Semiconductors
Objective specification
Bluetooth radio module
BGB110
FUNCTIONAL DESCRIPTION
Control
The BGB110 TrueBlue Bluetooth Radio Module is compatible with BlueRF unidirectional JTAG RXMODE 2. It can be
controlled directly by a Philips VW2600X family baseband processor, via an 8-wire control interface.
These 8 wires can be grouped into:
A four-wire serial JTAG interface for initialisation and general control of the radio module. The control signals are
SI_CDI (control data input), SI_CMS (control mode select), SI_CLK (control clock) and SI_CDO (control data output).
Three asynchronous control input signals SYS_CLK_REQ, PX_ON and SYNT_ON.
One asynchronous reset input signal POR_EXT.
These latter four wires control specific blocks inside the radio module.
Furthermore, the BGB110 supplies the baseband processor with four clock signals:
A 13 MHz system clock SYS_CLK, which can be switched off in order to save power.
A 1 MHz transmit clock TX_CLK, for clocking out the data to be transmitted.
A 3.2 kHz low-power clock for wake-up timing in the baseband processor.
A 2.048 MHz clock for PCM voice codecs.
JTAG interface
The JTAG serial interface is used to control the BGB110. The BGB110 has to be the only slave on the JTAG bus, it does
not allow for multi-slave operation. The JTAG interface protocol used is fully compliant with the standard set out in IEEE
Std 1149.1-1990. The following features are supported:
5-bit register address.
8-bit data.
Set instruction register.
Read/write data register (note that some addresses denote separate read and write data registers).
The JTAG interface allows for 2 ways of accessing a register. One is the communicate address and data, and the second
one is for successive accesses to the same register where only the data is communicated. This can e.g. be used for
updating the channel information before every packet.
S
TATE
D
IAGRAM
The state diagram is shown in Fig.3. Transitions from one state to another depend on the SI_CMS input at the rising edge
of SI_CLK. The SI_CMS and SI_CDI should change value at the falling edge of SI_CLK. Output SI_CDO will also change
at the falling edge of SI_CLK.
An instruction register scan (IR-Scan) period starts with a status information download (Capture-IR). The status inputs
to the instruction register are user-defined observability inputs. Afterwards, the data can be shifted out (Shift-IR), at the
same time as serial data/instruction are shifted in, or directly updated to the parallel output (Exit1-IR, Update-IR).
There is also a possibility for the IR-Scan period to be paused (Pause-IR) before a new data-shift. A data register scan
period is identical but there are no restrictions on the data during Capture-DR.