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| 型號(hào)： | AT85C51SND3B1-7FTUL |
| 廠商： | Atmel |
| 文件頁(yè)數(shù)： | 99/119頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC DECODER/ENCODER DGTL 100CBGA |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 類型： | 音頻編碼器/解碼器 |
| 應(yīng)用： | 移動(dòng)電話，手機(jī)，視頻顯示器 |
| 電壓 - 電源，數(shù)字： | 1.65 V ~ 3.6 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-TFBGA |
| 供應(yīng)商設(shè)備封裝： | 100-CTBGA（9x9） |
| 包裝： | 托盤(pán) |
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80
AT85C51SND3B
7632D–MP3–01/07
selected as source, the null device is always ready and sends the data (2 bytes) of the
initialized CRC value MSB first.
Channel Priority
The Data Flow Controller bandwidth is shared between Channel 0 and Channel 1. In
case both channels are ready to transfer data, bus bandwidth is shared on a byte by
byte basis.
In order to allocate maximum bandwidth to a specified channel, priority can be assigned
to channel 0 or to channel 1 by setting the DFPRIO1:0 bits in DFCON according to
DFPRIO1:0 can be modified at any time while transfer is on-going or not.
Table 93. Channel Priority Assignment
Data Flow Status
An on-going data flow transfer is reported to user using the bits DFBSY0 and DFBSY1
in DFCSTA. These bits are set as soon as the DFD has been fully written to the corre-
sponding channel and cleared at the end of transfer or abort.
Source peripheral and destination peripheral status is dynamically reported by SRDY0,
DRDY0, SRDY1, DRDY1 ready flags in DFCSTA.
Data Flow Abort
The DFC allows asynchronous abort of any on-going flow. Abort is controlled by the
DFABT0, DFABT1, the Channel Data Flow Abort control bits in DFCCON and DFABTM
the Data Flow Abort Mode control bit in DFCON.
Setting DFABT0 or DFABT1 while a flow transfer is on-going triggers on the correspond-
ing channel an immediate or delayed abort depending on the DFABTM value. DFABTM
cleared triggers an immediate abort where data flow transfer is stopped at the end of the
on-going byte transfer while DFABTM set triggers a delayed abort where data flow
transfer is stopped at the end of the on-going data packet transfer. Above abort modes
set the End of Flow interrupt flag of the corresponding channel.
Setting DFABT0 or DFABT1 while a DFD is under writing will reset the DFD content of
the corresponding channel. Such abort does not set the End of Flow interrupt flag of the
corresponding channel.
Abort Status
In case a data flow transfer is aborted, the remaining number of data packets to be
transmitted can be retrieved by reading two bytes with MSB first from the data flow
descriptor register DFD0 (channel 0) or to DFD1 (channel 1). This feature is of interest
in case of logical data flow management over a physical channel.
Note:
In case of immediate abort, returned value is not significant since part of the DP is
already transmitted.
DFPRIO1
DFPRIO0
Assignment Description
0
No priority assigned: channel 0 & channel 1 have same priority.
0
1
Priority assigned to channel 0.
1
0
Priority assigned to channel 1.
1
Reserved, do not set both bits.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AT85C51SND3B1N-DDV | 功能描述:音頻 DSP Microcontroller RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube |
| AT85C51SND3B1N-RTTUL | 功能描述:音頻 DSP Microcontroller RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube |
| AT85C51SND3B1-RTTUL | 功能描述:音頻 DSP MP3/WMA USB2.0 w/o DAC+DC/DC RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube |
| AT85C51SND3B2-RTTUL | 功能描述:音頻 DSP Microcontroller RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube |
| AT85C51SND3BX | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:MP3 Microcontrollers |
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