參數(shù)資料
型號: AT85C51SND3B1-7FTUL
廠商: Atmel
文件頁數(shù): 114/119頁
文件大?。?/td> 0K
描述: IC DECODER/ENCODER DGTL 100CBGA
標準包裝: 90
類型: 音頻編碼器/解碼器
應用: 移動電話,手機,視頻顯示器
電壓 - 電源,數(shù)字: 1.65 V ~ 3.6 V
安裝類型: 表面貼裝
封裝/外殼: 100-TFBGA
供應商設備封裝: 100-CTBGA(9x9)
包裝: 托盤
94
AT85C51SND3B
7632D–MP3–01/07
ID Detection
The ID pin transition is detected thanks to the following architecture:
Figure 58. ID Detection Input Block Diagram
By default, (no A-plug or B-plug), the macro is in the Peripheral mode (internal pull-up).
The IDTI interrupt is triggered when a A-plug (Host) is plugged or unplugged. The inter-
rupt is not triggered when a B-plug (Peripheral) is plugged or unplugged.
The IDTI interrupt may be triggered even if the USB controller is disabled.
Registers
USB general registers
R
P
U
UID
ID
USBSTA.1
Internal Pull Up
VDD
IDTI
USBINT.1
Table 102. USBCON Register
USBCON (1.E1h) – USB General Control Register
7
6
5
4
3
2
1
0
USBE
HOST
FRZCLK
OTGPADE
-
IDTE
VBUSTE
Bit
Number
Bit
Mnemonic Description
7
USBE
USB Controller Enable Bit
Set to enable the USB controller.
Clear to disable and reset the USB controller, to disable the USB transceiver and
to disable the USB controller clock inputs.
6
HOST
HOST Bit
Set to access to the Host registers.
Clear to access to the Device registers.
5
FRZCLK
Freeze USB Clock Bit
Set to disable the clock inputs (the “Resume Detection” is still active) and save
power consumption.
Clear to enable the clock inputs.
4
OTGPADE
OTG Pad Enable
Set to enable the OTG pad.
Clear to disable the OTG pad.
Note that this bit can be set/cleared even if USBE= 0 (this allows the VBUS
detection even if the USB macro is disable).
3-2
-
Reserved
The value read from these bits is always 0. Do not set these bits.
1
IDTE
ID Transition Interrupt Enable Bit
Set this bit to enable the ID Transition interrupt generation.
Clear this bit to disable the ID Transition interrupt generation.
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