參數(shù)資料
型號: AT85C51SND3B1-7FTUL
廠商: Atmel
文件頁數(shù): 26/119頁
文件大?。?/td> 0K
描述: IC DECODER/ENCODER DGTL 100CBGA
標準包裝: 90
類型: 音頻編碼器/解碼器
應用: 移動電話,手機,視頻顯示器
電壓 - 電源,數(shù)字: 1.65 V ~ 3.6 V
安裝類型: 表面貼裝
封裝/外殼: 100-TFBGA
供應商設(shè)備封裝: 100-CTBGA(9x9)
包裝: 托盤
14
AT85C51SND3B
7632D–MP3–01/07
MMI Interface
Table 13. Keypad Controller Signal Description
Table 14. LCD Interface Signal Description
Power Management
Table 15. Power Signal Description
TXD
O
Transmit Serial Data
TXD outputs the shift clock in serial I/O mode 0 and transmits data in
serial I/O modes 1, 2 and 3.
P3.1
MOSI
RTS
O
Request To Send Hardware Handshake Line
Asserted low by hardware when SIO is ready to receive data.
P3.2
INT0
SCK
CTS
I
Clear To Send Hardware Handshake Line
Asserted low by external hardware when SIO is allowed to send data.
P3.3
INT1
SS
Signal
Name
Type
Description
Alternate
Function
Signal
Name
Type
Description
Alternate
Function
KIN3:0
I
Keypad Input lines
Holding one of these pins high or low for 24 oscillator periods triggers a
keypad interrupt.
P1.3:0
Signal
Name
Type
Description
Alternate
Function
LD7:0
I/O
Display Data Bus
8-bit bidirectional data bus.
P0.7:0
SD7:0
LRD/LDE
O
Read Signal/Enable Signal
8080:
Read signal asserted low during display read access.
6800:
Enable signal asserted high during display access.
P5.0
SRD
LWR/LRW
O
Write Signal/Read Write Signal
8080:
Write signal asserted low during display write access.
6800:
Read/Write signal asserted low/high during display read/write
access
P5.3
SWR
LCS
O
Display Chip Select
Select signal asserted low during display access.
P5.1
SCS
LA0/LRS
O
Display Address Bit 0/Register Select
Address signal asserted during display access.
P5.2
SA0
Signal
Name
Type
Description
Alternate
Function
DCPWR
I
DC-DC Power ON Input
Connect DCPWR to V
SS to start the DC-DC converter.
-
DCLI
PWR
DC-DC Inductance Input
Connect low ESR inductance to DCLI and BVDD.
BVDD
PWR
Battery Supply Voltage
Connect this pin to the positive pin of the battery.
-
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