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參數(shù)資料
| 型號(hào)： | AT85C51SND3B1-7FTUL |
| 廠商： | Atmel |
| 文件頁(yè)數(shù)： | 23/119頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC DECODER/ENCODER DGTL 100CBGA |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 類型： | 音頻編碼器/解碼器 |
| 應(yīng)用： | 移動(dòng)電話，手機(jī)，視頻顯示器 |
| 電壓 - 電源，數(shù)字： | 1.65 V ~ 3.6 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-TFBGA |
| 供應(yīng)商設(shè)備封裝： | 100-CTBGA（9x9） |
| 包裝： | 托盤 |
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119
AT85C51SND3B
7632D–MP3–01/07
Reset Value = 0000 0000b
Table 120. UERST Register
UERST (1.CAh) – USB Endpoint Reset Register
7
6
5
4
3
2
1
0
-
EPRST6
EPRST5
EPRST4
EPRST3
EPRST2
EPRST1
EPRST0
Bit
Number
Bit
Mnemonic Description
7
-
Reserved
The value read from these bits is always 0. Do not set these bits.
6-0
EPRST6:0
Endpoint FIFO Reset Bits
Set to reset the selected endpoint FIFO prior to any other operation, upon
hardware reset or when an USB bus reset has been received. See
Section “Endpoint Reset” for more information.
Then, cleared by software to complete the reset operation and start using the
FIFO.
Table 121. UECONX Register
UECONX (1.CBh) – USB Endpoint Control Register
7
6
5
4
3
2
1
0
-
STALLRQ
STALLRQC
RSTDT
EPNUMS
DFCRDY
EPEN
Bit
Number
Bit
Mnemonic Description
7-6
-
Reserved
The value read from these bits is always 0. Do not set these bits.
5
STALLRQ
STALL Request Handshake Bit
Set to request a STALL answer to the host for the next handshake.
Cleared by hardware when a new SETUP is received. Clearing by software has
no effect.
See Section “STALL Request” for more details.
4
STALLRQC
STALL Request Clear Handshake Bit
Set to disable the STALL handshake mechanism.
Cleared by hardware immediately after the set. Clearing by software has no
effect.
See Section “STALL Request” for more details.
3
RSTDT
Reset Data Toggle Bit
Set to automatically clear the data toggle sequence:
For OUT endpoint: the next received packet will have the data toggle 0.
For IN endpoint: the next packet to be sent will have the data toggle 0.
Cleared by hardware instantaneously. The firmware does not have to wait that
the bit is cleared. Clearing by software has no effect.
2
EPNUMS
Endpoint Number Select Bit
Set to configure the EPNUM used by the DFC.
Clear to select the EPNUM used by the CPU.
1
DFCRDY
DFC Ready Bit
Set to resume/enable the DFC interface.
Clear to pause the DFC interface.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AT85C51SND3B1N-DDV | 功能描述:音頻 DSP Microcontroller RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube |
| AT85C51SND3B1N-RTTUL | 功能描述:音頻 DSP Microcontroller RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube |
| AT85C51SND3B1-RTTUL | 功能描述:音頻 DSP MP3/WMA USB2.0 w/o DAC+DC/DC RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube |
| AT85C51SND3B2-RTTUL | 功能描述:音頻 DSP Microcontroller RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube |
| AT85C51SND3BX | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:MP3 Microcontrollers |
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