參數(shù)資料
型號(hào): AT85C51SND3B1-7FTUL
廠商: Atmel
文件頁數(shù): 117/119頁
文件大小: 0K
描述: IC DECODER/ENCODER DGTL 100CBGA
標(biāo)準(zhǔn)包裝: 90
類型: 音頻編碼器/解碼器
應(yīng)用: 移動(dòng)電話,手機(jī),視頻顯示器
電壓 - 電源,數(shù)字: 1.65 V ~ 3.6 V
安裝類型: 表面貼裝
封裝/外殼: 100-TFBGA
供應(yīng)商設(shè)備封裝: 100-CTBGA(9x9)
包裝: 托盤
97
AT85C51SND3B
7632D–MP3–01/07
Reset Value = 0000 0000b
5
HNPREQ
HNP Request Bit
Set to initiate the HNP when the controller is in the Device mode (B).
Set to accept the HNP when the controller is in the Host mode (A).
Cleared by hardware after the HNP completion.
4
SRPREQ
SRP Request Bit
Set to initiate the SRP when the controller is in Device mode.
Cleared by hardware when the controller is initiating a SRP.
3
SRPSEL
SRP Selection Bit
Set to choose VBUS pulsing as SRP method.
Clear to choose data line pulsing as SRP method.
2
VBUSHWC
VBus Hardware Control Bit
Set to disable the hardware control over the UVCON pin.
Clear to enable the hardware control over the UVCON pin.
1
VBUSREQ
VBUS Request Bit
Set to assert the UVCON pin in order to enable the VBUS power supply
generation. This bit shall be used when the controller is in the Host mode.
Cleared by hardware when VBUSRQC is set.
0
VBUSRQC
VBUS Request Clear Bit
Set to deassert the UVCON pin in order to enable the VBUS power supply
generation. This bit shall be used when the controller is in the Host mode.
Cleared by hardware immediately after the set.
Table 108. OTGTCON Register
OTGTCON (1.E6h) – USB OTG Timer Control Register
7
6
5
4
3
2
1
0
1
PAGE1:0
-
VALUE2:0
Bit
Number
Bit
Mnemonic Description
7
1
OTGTCON Pagination
This bit must be set to access the OTGTCON register.
6-5
PAGE1:0
Timer Page Access Bit
Set/clear to access a special timer register.
4-3
-
Reserved
The value read from these bits is always 0. Do not set these bits.
2-0
VALUE2:0
Value Bit
Set to initialize the new value of the timer.
Bit
Number
Bit
Mnemonic Description
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