參數(shù)資料
型號(hào)： AT43USB320A-AC
廠商： ATMEL CORP
元件分類： 微控制器/微處理器
英文描述： Full-speed USB Microcontroller with an Embedded Hub
中文描述： 8-BIT, 12 MHz, RISC MICROCONTROLLER, PQFP100
封裝： 14 X 14 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, MS-026AED, LQFP-100
文件頁數(shù)： 94/115頁
文件大?。?/td> 722K
代理商： AT43USB320A-AC
94
AT43USB320A
1443E–USB–4/04
Hub Port Status Change Register – PSCR1..3
The microcontroller firmware uses the bits in this register to monitor when a port status change
has occurred, which then gets reported to the host through the Port Change Field
wPortChange.
Except for bit 3, the Port Overcurrent Indicator Change, the bits in this register are set by the
USB hardware. Otherwise, the firmware should only clear these bits.
Bit 7..5 – Reserved
These bits are reserved in the AT43USB320A and will read as zero.
Bit 4 – RSTSC: Port Reset Status Change
0 = No change
1 = Reset complete
This bit is set by the USB hardware after it completes RESET signaling which is initiated when
the Reset and Enable Port command is detected at the Port Control Register, HPCON. The
firmware sends this command when it decodes a SetPortFeature(PORT_RESET) request
from the host.
At EOF2 after the hardware completes the port reset, the hardware sets the Port Enable Sta-
tus bit and clears the Port Reset Status bit of the Hub Port Status Register, HPSTAT. Cleared
by firmware, ClearPortFeature(PORT_RESET).
Bit 3 – POCIC: Port Overcurrent Indicator Change
0 = No change has occurred on Overcurrent Indicator
1 = Overcurrent Indicator has changed
This bit is relevant to hubs with individual overcurrent reporting only. The firmware sets this bit
as a result of detecting overcurrent at the ports OVC# pin. The firmware clears bit through
ClearPortFeature(PORT_OVER_CURRENT). For Port 1, this bit is always cleared.
Bit 2 – PSSC: Port Suspend Status Change
0 = No change
1 = Resume completed
Port 1:4 is set by hardware upon completion of firmware initiated resume process. Port 5 is set
by firmware 20 ms after the next EOF2 after completion of resume process. RESUME signal-
ing is initiated through global resume, selective resume and remote wakeup. Cleared by
firmware via host request ClearPortFeature(PORT_SUSPEND).
Bit
7
6
5
4
3
2
1
0
Port1 $1FB0
–
–
–
RSTSC
POCIC
PSSC
PESC
PCSC
PSCR1
Port2 $1FB1
–
–
–
RSTSC
POCIC
PSSC
PESC
PCSC
PSCR2
Port3 $1FB2
–
–
–
RSTSC
POCIC
PSSC
PESC
PCSC
PSCR3
Port4 $1FB3
–
–
–
RSTSC
POCIC
PSSC
PESC
PCSC
PSCR4
Port5 $1FB4
–
–
–
RSTSC
POCIC
PSSC
PESC
PCSC
PSCR5
Read/Write
R
R
R
R
R
R
R
R
Initial Value
0
0
0
0
0
0
0
0
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