參數(shù)資料
型號: AT43USB320A-AC
廠商: ATMEL CORP
元件分類: 微控制器/微處理器
英文描述: Full-speed USB Microcontroller with an Embedded Hub
中文描述: 8-BIT, 12 MHz, RISC MICROCONTROLLER, PQFP100
封裝: 14 X 14 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, MS-026AED, LQFP-100
文件頁數(shù): 22/115頁
文件大小: 722K
代理商: AT43USB320A-AC
22
AT43USB320A
1443E–USB–4/04
Figure 5.
AT43USB320A Interrupt Structure
Reset Sources
The AT43USB320A has four sources of reset:
Power-on Reset
– The MCU is reset when the supply voltage is below the power-on reset
threshold.
External Reset
– The MCU is reset when a low level is present on the RESET pin for
more than 50 ns.
Watchdog Reset
– The MCU is reset when the watchdog timer period expires and the
watchdog is enabled.
USB Reset
– A USB bus reset is defined as a SE0 (single ended zero) of at least 4 slow
speed USB clock cycles received by Port0. The internal reset pulse to the USB hardware
and microcontroller lasts for 24 oscillator periods.
When the USB hardware is reset, the compound device is de-configured and has to be re-
enumerated by the host. When the microcontroller is reset, all I/O registers are then set to their
initial values, and the program starts execution from address $000. The instruction placed in
address $000 must be a JMP instruction to the reset handling routine. If the program never
enables an interrupt source, the interrupt vectors are not used, and regular program code can
be placed at these locations. The circuit diagram in Figure 6 shows the reset logic. The user
can select the start-up time according to typical oscillator start-up. The number of WDT oscilla-
tor cycles used for each time-out is shown in Table 7.
Suspend/Resume
Register
Suspend/Resume
Interrupt Enable
Register
USB Interrupt
Status Register
USB Interrupt
Enable Register
USB
UART UDRE
SPI STC
TIMER0 OVF
TIMER1 OVF
TIMER1 COMPB
TIMER1 COMPA
TIMER1 CAPT
INT1
INT0, SUSP/RSM
RESET
Microcontroller
Interrupt
Logic
13
12
9
8
7
6
5
4
3
2
1
SOF
EOF2
FEP2
FEP1
FEP0
RESERVED
HEP0
FRMWUP
RSM
GLB SUSP
UART RX
10
11
UART TX
EOF1
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