參數(shù)資料
型號: AT43USB320A-AC
廠商: ATMEL CORP
元件分類: 微控制器/微處理器
英文描述: Full-speed USB Microcontroller with an Embedded Hub
中文描述: 8-BIT, 12 MHz, RISC MICROCONTROLLER, PQFP100
封裝: 14 X 14 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, MS-026AED, LQFP-100
文件頁數(shù): 51/115頁
文件大?。?/td> 722K
代理商: AT43USB320A-AC
51
AT43USB320A
1443E–USB–4/04
Watchdog Timer Control Register – WDTCR
Bits 7..5 –Res: Reserved Bits
These bits are reserved bits in the AT43USB320A and will always read as zero.
Bit 4 –WDTOE: Watch Dog Turn-Off Enable
This bit must be set (one) when the WDE bit is cleared. Otherwise, the watchdog will not be
disabled. Once set, the hardware will clear this bit to zero after four clock cycles. Refer to the
description of the WDE bit for a watchdog disable procedure.
Bit 3 –WDE: Watch Dog Enable
When the WDE is set (one) the Watchdog Timer is enabled, and if the WDE is cleared (zero)
the Watchdog Timer function is disabled. WDE can only be cleared if the WDTOE bit is set
(one). To disable an enabled watchdog timer, the following procedure must be followed:
1.
In the same operation, write a logical one to WDTOE and WDE. A logical one must be
written to WDE even though it is set to one before the disable operation starts.
2.
Within the next four clock cycles, write a logical 0 to WDE. This disables the watchdog.
Bits 2..0 –WDP2, WDP1, WDP0: Watch Dog Timer Prescaler 2, 1 and 0
The WDP2, WDP1 and WDP0 bits determine the Watchdog Timer prescaling when the
Watchdog Timer is enabled. The different prescaling values and their corresponding Time-out
Periods are shown in Table 19.
Note:
The WDR (Watchdog Reset) instruction should always be executed before the Watchdog Timer
is enabled. This ensures that the reset period will be in accordance with the Watchdog Timer
prescale settings. If the Watchdog Timer is enabled without reset, the watchdog timer may not
start to count from zero. To avoid unintentional MCU reset, the Watchdog Timer should be dis-
abled or reset before changing the Watchdog Timer Prescale Select.
Bit
7
6
5
4
3
2
1
0
$21 ($41)
WDTOE
WDE
WDP2
WDP1
WDP0
WDTCR
Read/Write
R
R
R
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
Table 19.
Watchdog Timer Prescale Select
WDP2
WDP1
WDP0
Number of WDT Oscillator cycles
Time-out
0
0
0
8K cycles
8.2 ms
0
0
1
16K cycles
16.4 ms
0
1
0
32K cycles
33.8 ms
0
1
1
64K cycles
65.6 ms
1
0
0
128K cycles
0.131 s
1
0
1
256K cycles
0.262 s
1
1
0
512K cycles
0.524 s
1
1
1
1,024K cycles
1.048 s
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