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參數(shù)資料
| 型號： | AT43USB320A-AC |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Full-speed USB Microcontroller with an Embedded Hub |
| 中文描述： | 8-BIT, 12 MHz, RISC MICROCONTROLLER, PQFP100 |
| 封裝： | 14 X 14 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, MS-026AED, LQFP-100 |
| 文件頁數(shù)： | 56/115頁 |
| 文件大小： | 722K |
| 代理商： | AT43USB320A-AC |
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56
AT43USB320A
1443E–USB–4/04
SPI Control Register – SPCR
Bit 7 –SPIE: SPI Interrupt Enable
This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR register is set and the
global interrupts are enabled.
Bit 6 –SPE: SPI Enable
When the SPE bit is set (one), the SPI is enabled. This bit must be set to enable any SPI
operations.
Bit 5 –DORD: Data Order
When the DORD bit is set (one), the LSB of the data word is transmitted first.
When the DORD bit is cleared (zero), the MSB of the data word is transmitted first.
Bit 4 –MSTR: Master/Slave Select
This bit selects Master SPI mode when set (one), and Slave SPI mode when cleared (zero). If
SS is configured as an input and is driven low while MSTR is set, MSTR will be cleared, and
SPIF in SPSR will become set. The user will then have to set MSTR to re-enable SPI master
mode.
Bit 3 –CPOL: Clock Polarity
When this bit is set (one), SCK is high when idle. When CPOL is cleared (zero), SCK is low
when idle. Refer to Figure 17 and Figure 18 for additional information.
Bit 2 –CPHA: Clock Phase
Refer to Figure 17 or Figure 18 for the functionality of this bit.
Bits 1,0 –SPR1, SPR0: SPI Clock Rate Select 1 and 0
These two bits control the SCK rate of the device configured as a master. SPR1 and SPR0
have no effect on the slave. The relationship between SCK and the Oscillator Clock frequency
f
CL
is shown in the following table:
Bit
7
6
5
4
3
2
1
0
$0D ($2D)
SPIE
SPE
DORD
MSTR
CPOL
CPHA
SPR1
SPR0
SPCR
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
Table 21.
Relationship Between SCK and the Oscillator Frequency
SPR1
SPR0
SCK Frequency
0
0
3 MHz
0
1
750 kHz
1
0
187.5 kHz
1
1
93.75 kHz
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相關(guān)代理商/技術(shù)參數(shù) |
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