參數(shù)資料
型號: AT43USB320A-AC
廠商: ATMEL CORP
元件分類: 微控制器/微處理器
英文描述: Full-speed USB Microcontroller with an Embedded Hub
中文描述: 8-BIT, 12 MHz, RISC MICROCONTROLLER, PQFP100
封裝: 14 X 14 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, MS-026AED, LQFP-100
文件頁數(shù): 69/115頁
文件大小: 722K
代理商: AT43USB320A-AC
69
AT43USB320A
1443E–USB–4/04
Port D as General
Digital I/O
PDn, General I/O Pin:
The DDDn bit in the DDRD register selects the direction of this pin. If
DDDn is set (one), PDn is con-figured as an output pin. If DDDn is cleared (zero), PDn is con-
figured as an input pin. If PORTDn is set (one) when the pin is configured as an input pin, the
MOS pull-up resistor is activated. To switch the pull-up resistor off, the PORTDn has to be
cleared (zero) or the pin has to configured as an output pin. The Port D pins are tri-stated
when a reset condition becomes active, even if the clock is not active.
Note:
n: 7, 6...0, pin number.
Programming
the USB Module
The USB hardware consists of two devices, hub and function, each with their own device
address and endpoints. Its operation is controlled through a set of memory mapped registers.
The exact configuration of the USB device is defined by the software and it can be pro-
grammed to operate as a compound device, or as a hub only or as a function only. The hub
has the required control and interrupt endpoints. The number of external downstream ports is
programmable from 0 to 4. The DP and DM pins of the unused port(s) must be connected to
ground. The USB function has one control endpoint and 2 programmable endpoints. All the
endpoints have their own 8-byte FIFO. If the hub is disabled, one extra endpoint becomes
available to the function.
The USB Function
The USB function hardware is designed to operate in the single packet mode and to manage
the USB protocol layer. It consists of a Serial Interface Engine (SIE), endpoint FIFOs and a
Function Interface Unit (FIU). The SIE performs the following tasks: USB signaling detec-
tion/generation, data serialization/de-serialization, data encoding/decoding, bit stuffing and un-
stuffing, clock/data separation, and CRC generation/checking. It also decodes and manages
all packet data types and packet fields.
The endpoint FIFO buffers the data to be sent out or data received. The FIU manages the flow
of data between the SIE, FIFO and the internal microcontroller bus. It controls the FIFO and
monitors the status of the transactions and interfaces to the CPU. It initiates interrupts and
acts upon commands sent by the firmware.
The USB function hardware of the AT43USB320A makes the physical interface and the proto-
col layer transparent to the user. To start the process, the firmware must first enable the
endpoints and which place them in receive mode by default. The device address by default is
address 0. The USB function hardware then waits for a setup token from the host. When a
valid the setup token is received, it automatically stores the data packet in endpoint 0 FIFO
and responds with an ACK. It then notifies the microcontroller through an interrupt. The micro-
controller reads the FIFO and parses the request.
Transactions for the non-control endpoints are even simpler. Once the endpoint is enabled, it
waits for an IN or an OUT token depending whether it is programmed as an IN or OUT end-
point. For example, if it is an IN endpoint, the microcontroller simply loads the data into the
endpoint's FIFO and sets a bit in the control and status register. The USB hardware will
assemble the data in a USB packet and waits for an IN token. When it receives one, it auto-
matically responds by transmitting the data packet and completes the transaction by waiting
for the host's ACK. When one is received, the USB hardware will signal the microcontroller
Table 28.
DDDn Bits on Port D Pins
DDDn
PORTDn
I/O
Comment
0
0
Input
Tri-state (Hi-Z)
0
1
Input
Tri-state (Hi-Z)
1
0
Output
Push-Pull Zero Output
1
1
Output
Push-Pull One Output
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