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| 型號(hào)： | AT43USB320A-AC |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Full-speed USB Microcontroller with an Embedded Hub |
| 中文描述： | 8-BIT, 12 MHz, RISC MICROCONTROLLER, PQFP100 |
| 封裝： | 14 X 14 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, MS-026AED, LQFP-100 |
| 文件頁(yè)數(shù)： | 64/115頁(yè) |
| 文件大?。?/td> | 722K |
| 代理商： | AT43USB320A-AC |
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64
AT43USB320A
1443E–USB–4/04
(PINA) $19($39). The Port A Input Pins address is read only, while the Data Register and the
Data Direction Register are read/write.
The port pins have no selectable pull-up resistors.
Port A Data Register – PORTA
Port A Data Direction Register – DDRA
Port A Input Pins Address – PINA
The Port A Input Pins address (PINA) is not a register, and this address enables access to the
physical value on each Port A pin. When reading PORTA the Port A Data Latch is read, and
when reading PINA, the logical values present on the pins are read.
Port A as General
Digital I/O
All 8 pins in Port A have equal functionality when used as digital I/O pins.
PAn, General I/O Pin:
The DDAn bit in the DDRA register selects the direction of this pin, if
DDAn is set (one), PAn is configured as an output pin. If DDAn is cleared (zero), PAn is config-
ured as an input pin. If PORTAn is set (one) when the pin is configured as an input pin, the
MOS pull-up resistor is activated. To switch the pull-up resistor off, the PORTAn has to be
cleared (zero) or the pin has to configured as an output pin. The Port A pins are tri-stated
when a reset condition becomes active, even if the clock is not active.
Note:
n: 7,6...0, pin number.
Port B
Port B is an 8-bit bi-directional I/O port. The Port B output buffers can sink or source 4 mA.
Bit
7
6
5
4
3
2
1
0
$1B ($3B)
PORTA7
PORTA6
PORTA5
PORTA4
PORTA3
PORTA2
PORTA1
PORTA0
PORTA
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
$1A ($3A)
DDA7
DDA6
DDA5
DDA4
DDA3
DDA2
DDA1
DDA0
DDRA
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
$19 ($39)
PINA7
PINA6
PINA5
PINA4
PINA3
PINA2
PINA1
PINA0
PINA
Read/Write
R
R
R
R
R
R
R
R
Initial Value
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Table 23.
DDAn Effects on Port A Pins
DDAn
PORTAn
I/O
Comment
0
0
Input
Tri-state (Hi-Z)
0
1
Input
Tri-state (Hi-Z)
1
0
Output
Push-Pull Zero Output
1
1
Output
Push-Pull One Output
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相關(guān)代理商/技術(shù)參數(shù) |
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