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參數(shù)資料
| 型號： | ASM5I9658G-32-LR |
| 廠商： | ALLIANCE SEMICONDUCTOR CORP |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 3.3V 1:10 LVCMOS PLL Clock Generator |
| 中文描述： | 9658 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封裝： | 7 X 7 MM, GREEN, LQFP-32 |
| 文件頁數(shù)： | 9/14頁 |
| 文件大小： | 579K |
| 代理商： | ASM5I9658G-32-LR |
July 2005
rev 0.2
ASM5I9658
3.3V 1:10 LVCMOS PLL Clock Generator
9 of
14
Notice: The information in this document is subject to change without notice.
Driving Transmission Lines
The ASM5I9658 clock driver was designed to drive high
speed signals in a terminated transmission line
environment. To provide the optimum flexibility to the
user the output drivers were designed to exhibit the
lowest impedance possible. With an output impedance of
less than 20
the drivers can drive either parallel or
series terminated transmission lines. In most high
performance clock networks point-to-point distribution of
signals is the method of choice. In a point-to-point
scheme either series terminated or parallel terminated
transmission lines can be used. The parallel technique
terminates the signal at the end of the line with a 50
resistance to V
CC
÷2.
This technique draws a fairly high level of DC current and
thus only a single terminated line can be driven by each
output of the ASM59658 clock driver. For the series
terminated case however there is no DC current draw,
thus the outputs can drive multiple series terminated
lines. Figure 6. “Single versus Dual Transmission Lines”
illustrates an output driving a single series terminated line
versus two series terminated lines in parallel. When taken
to its extreme the fanout of the ASM5I9658 clock driver is
effectively doubled due to its capability to drive multiple
lines.
Figure 6. Single versus Dual Transmission Lines
The waveform plots in Figure 7. “Single versus Dual Line
Termination Waveforms” show the simulation results of
an output driving a single line versus two lines. In both
cases the drive capability of the ASM5I9658 output buffer
is more than sufficient to drive 50
transmission lines on
the incident edge. Note from the delay measurements in
the simulations a delta of only 43pS exists between the
two differently loaded outputs. This suggests that the dual
line driving need not be used exclusively to maintain the
tight output-to-output skew of the ASM5I9658. The output
waveform in Figure 7. “Single versus Dual Line
Termination Waveforms” shows a step in the waveform,
this step is caused by the impedance mismatch seen
looking into the driver. The parallel combination of the
36
series resistor plus the output impedance does not
match the parallel combination of the line impedances.
The voltage wave launched down the two lines will equal:
V
L
= V
S
( Z
0
÷
(R
S
+R
0
+Z
0
))
Z
0
= 50
|| 50
R
S
= 36
|| 36
R
0
= 14
V
L
= 3.0 ( 25 ÷(18+14+25))
= 1.31V
At the load end the voltage will double, due to the near
unity reflection coefficient, to 2.6V. It will then increment
towards the quiescent 3.0V in steps separated by one
round trip delay (in this case 4.0nS).
Figure 7. Single versus Dual Waveforms
Since this step is well above the threshold region it will
not cause any false clock triggering, however designers
may be uncomfortable with unwanted reflections on the
line. To better match the impedances when driving
multiple lines the situation in Figure 8. “Optimized Dual
Line Termination” should be used. In this case the series
terminating resistors are reduced such that when the
parallel combination is added to the output buffer
impedance the line impedance is perfectly matched.
14
+ 22
|| 22
= 50
|| 50
25
= 25
Figure 8. Optimized Dual Line Termination
ASM5I9658
OUTPUT BUFFER
14
IN
OUTA
Z
0
=50
R
S
=36
ASM5I9658
OUTPUT BUFFER
14
IN
OUTB1
Z
0
=50
R
S
=36
OUTB0
Z
0
=50
R
S
=36
ASM5I9658
OUTPUT BUFFER
14
IN
Z
0
=50
R
S
=22
Z
0
=50
R
S
=22
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ASM5I9658 | 3.3V 1:10 LVCMOS PLL Clock Generator |
| ASM5I9658-32-ER | 3.3V 1:10 LVCMOS PLL Clock Generator |
| ASM5I9772A | 2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
| ASM5I9772A-52-ER | 2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
| ASM5I9772A-52-ET | 2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ASM5I9772A | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
| ASM5I9772A-52-ER | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
| ASM5I9772A-52-ET | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
| ASM5I9772AG-52-ER | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
| ASM5I9772AG-52-ET | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
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