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參數(shù)資料
| 型號(hào)： | ASM5I9658G-32-LR |
| 廠商： | ALLIANCE SEMICONDUCTOR CORP |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | 3.3V 1:10 LVCMOS PLL Clock Generator |
| 中文描述： | 9658 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封裝： | 7 X 7 MM, GREEN, LQFP-32 |
| 文件頁(yè)數(shù)： | 5/14頁(yè) |
| 文件大?。?/td> | 579K |
| 代理商： | ASM5I9658G-32-LR |
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July 2005
rev 0.2
Table 5: DC CHARACTERISTICS
(V
CC
= 3.3V ± 5%, T
A
= 0°C to 70°C)
ASM5I9658
3.3V 1:10 LVCMOS PLL Clock Generator
5 of
14
Notice: The information in this document is subject to change without notice.
Symbol
V
IH
V
IL
Characteristics
Input high voltage
Input low voltage
Peak-to-peak input voltage
(PCLK)
Common Mode Range
(PCLK)
Output High Voltage
Output Low Voltage
3
Min
2.0
Typ
Max
V
CC
+0.3
0.8
Unit
V
V
mV
Condition
LVCMOS
LVCMOS
LVPECL
V
PP
250
V
CMR
1
1.0
V
CC
-0.6
V
LVPECL
V
OH
2.4
V
V
V
I
OH
=-24 mA
2
V
OL
0.55
0.30
I
OL
=24mA
I
OL
=12mA
Z
OUT
I
IN
I
CC_PLL
I
CCQ
Note: 1. V
CMR
(DC) is the cross point of the differential input signal. Functional operation is obtained ,when the crosspoint is within the V
CMR
range and the input swing lies within the V
PP
(DC) specification.
2.The ASM3P9658 is capable of driving 50
transmission lines on the incident edge. Each output drives one 50
parallel terminated
transmission line to a termination voltage of V
TT
. Alternatively, the device drives up to two 50
series terminated transmission lines.
3.The ASM5I9658 output levels are compatible to the MPC958 output levels.
4.Inputs have pull-down or pull-up resistors affecting the input current.
Output impedance
Input Current
4
Maximum PLL Supply Current
Maximum Quiescent Supply Current
14 -17
μA
mA
mA
±200
15
15
V
IN
=V
CC
or GND
V
CC_PLL
Pin
All V
CC
Pins
12
13
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ASM5I9658 | 3.3V 1:10 LVCMOS PLL Clock Generator |
| ASM5I9658-32-ER | 3.3V 1:10 LVCMOS PLL Clock Generator |
| ASM5I9772A | 2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
| ASM5I9772A-52-ER | 2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
| ASM5I9772A-52-ET | 2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ASM5I9772A | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
| ASM5I9772A-52-ER | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
| ASM5I9772A-52-ET | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
| ASM5I9772AG-52-ER | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
| ASM5I9772AG-52-ET | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
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