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參數(shù)資料
| 型號： | ASM5I9658G-32-LR |
| 廠商： | ALLIANCE SEMICONDUCTOR CORP |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 3.3V 1:10 LVCMOS PLL Clock Generator |
| 中文描述： | 9658 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封裝： | 7 X 7 MM, GREEN, LQFP-32 |
| 文件頁數(shù)： | 6/14頁 |
| 文件大小： | 579K |
| 代理商： | ASM5I9658G-32-LR |
July 2005
rev 0.2
Table 6: AC CHARACTERISTICS
(V
CC
= 3.3V ± 5%, T
A
= 0°C to 70°C)
1
Symbol
Characteristics
Input reference frequency ÷2 feedback
2
PLL mode, external feedback ÷4 feedback
3
Input reference frequency in PLL bypass mode
4
f
VCO
VCO operating frequency range
5
Output Frequency ÷2 feedback
3
ASM5I9658
3.3V 1:10 LVCMOS PLL Clock Generator
6 of
14
Notice: The information in this document is subject to change without notice.
Min
100
50
0
200
100
50
Typ
Max
250
125
250
500
250
125
Unit
MHz
MHz
MHz
MHz
MHz
MHz
Condition
PLL locked
PLL locked
f
REF
PLL locked
PLL locked
f
MAX
÷4 feedback
4
V
PP
Peak-to-peak input voltage
PCLK
Common Mode Range
PCLK
Input Reference Pulse Width
7
Propagation Delay (static phase offset)
8
PCLK to
FB_IN
500
1000
mV
LVPECL
V
CMR
6
1.2
VCC-0.9
V
LEPVCL
t
PW,MIN
2
nS
t
()
f
REF
=100MHz
any frequency
-70
-125
+80
+125
pS
pS
PLL locked
t
PD
Propagation Delay PLL and divider bypass,
PCLK to Q0-9
Output-to-output Skew
9
Output duty cycle
10
1.0
(T÷2)-
400
0.1
4.0
120
(T÷2)+4
00
1.0
7.0
6.0
80
80
5.5
6.5
nS
pS
t
sk(O)
DC
T÷2
pS
t
R
,t
F
t
PLZ, HZ
t
PZL, LZ
t
JIT(CC)
t
JIT(PER)
Output Rise/Fall Time
Output Disable Time
Output Enable Time
Cycle-to-cycle jitter
Period Jitter
I/O Phase Jitter
f
VCO
=500 MHz and ÷ 2 feedback, RMS (1
σ
)
11
f
VCO
=500 MHz and ÷ 4 feedback, RMS (1
σ
)
PLL closed loop bandwidth
12
÷
2 feedback
8
PLL mode, external feedback ÷4 feedback
9
Maximum PLL Lock Time
Note:1. AC characteristics apply for parallel output termination of 50
to V
TT
.
2. ÷2 PLL feedback (high frequency range) requires VCO_SEL=0, PLL_EN=1, BYPASS=1 and MR/OE=0.
3.÷4 PLL feedback (low frequency range) requires VCO_SEL=1, PLL_EN=1, BYPASS=1 and MR/OE=0.
4.In bypass mode, the ASM3P9658 divides the input reference clock.
5.The input frequency f
must match the VCO frequency range divided by the feedback divider ratio FB: f
= f
÷ FB.
6.V
CMR
(AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR
range and the input swing lies within the V
(AC) specification. Violation of VCMR or VPP impacts static phase offset t().
7.Calculation of reference duty cycle limits: DC
REF
,MIN = tPW,MIN . f
REF
. 100% and DCREF,MAX = 100% - DC
REF
,MIN.
8.Valid for f
REF
=50 MHz and FB=÷8 (VCO_SEL=1). For other reference frequencies: t() [pS] = 50 pS ± (1÷(120 . f
REF
)).
9.See application section for part-to-part skew calculation in PLL zero-delay mode.
10.Output duty cycle is DC = (0.5 ± 400 pS. f
OUT
) V 100%. E.g. the DC range at f
OUT
=100MHz is 46%<DC<54%. T = output period.
11.See application section for a jitter calculation for other confidence factors than 1 and a characteristic for other VCO frequencies.
12.-3 dB point of PLL transfer characteristics.
nS
nS
nS
pS
pS
pS
pS
MHz
MHz
mS
0.55 to 2.4V
t
JIT()
BW
6-20
2 - 8
t
LOCK
10
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ASM5I9658 | 3.3V 1:10 LVCMOS PLL Clock Generator |
| ASM5I9658-32-ER | 3.3V 1:10 LVCMOS PLL Clock Generator |
| ASM5I9772A | 2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
| ASM5I9772A-52-ER | 2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
| ASM5I9772A-52-ET | 2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ASM5I9772A | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
| ASM5I9772A-52-ER | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
| ASM5I9772A-52-ET | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
| ASM5I9772AG-52-ER | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
| ASM5I9772AG-52-ET | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
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