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參數(shù)資料
| 型號： | ASM5I9658G-32-LR |
| 廠商： | ALLIANCE SEMICONDUCTOR CORP |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | 3.3V 1:10 LVCMOS PLL Clock Generator |
| 中文描述： | 9658 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封裝： | 7 X 7 MM, GREEN, LQFP-32 |
| 文件頁數(shù)： | 3/14頁 |
| 文件大?。?/td> | 579K |
| 代理商： | ASM5I9658G-32-LR |
July 2005
rev 0.2
Table 1: Pin Configuration
ASM5I9658
3.3V 1:10 LVCMOS PLL Clock Generator
3 of
14
Notice: The information in this document is subject to change without notice.
Pin #
6
7
2
32
Pin Name
PCLK,
PCLK
FB_IN
VCO_SEL
BYPASS
PLL_EN
MR/OE
I/O
Type
Function
Input
LVPECL
LVPECL reference clock signal
Input
Input
LVCMOS
LVCMOS
PLL feedback signal input, connect to QFB
Operating frequency range select
3
Input
LVCMOS
PLL and output divider bypass select
4
Input
LVCMOS
PLL enable/disable
5
Input
LVCMOS
Output enable/disable (high-impedance tristate) and device reset
28,26,24,
22,20,18,
16,14,12,
10
30
8,9,13,17
21,25,29
Q0-9
Output
LVCMOS
Clock outputs
QFB
Output
LVCMOS
Clock output for PLL feedback, connect to FB_IN
GND
Supply
Ground
Negative power supply (GND)
1
VCC_PLL
Supply
VCC
PLL positive power supply (analog power supply). It is recommended
to use an external RC filter for the analog power supply pin V
CC_PLL
.
Please see applications section for details.
Positive power supply for I/O and core. All V
CC
pins must be connected
to the positive power supply for correct operation
11,15,19,
23,27,31
VCC
Supply
VCC
Table 2: FUNCTION TABLE
Control
Default
0
1
PLL_EN
1
Test mode with PLL bypassed. The reference
clock (PCLK) is substituted for the internal VCO
output. ASM59658 is fully static and no minimum
frequency limit applies. All PLL related AC
characteristics are not applicable.
Selects the VCO output
1
BYPASS
1
Test mode with PLL and output dividers
bypassed. The reference clock (PCLK) is directly
routed to the outputs. ASM59658 is fully static
and no minimum frequency limit applies. All PLL
related AC characteristics are not applicable.
Selects the output dividers.
VCO_SEL
1
VCO ÷ 1 (High frequency range).
f
REF
= f
Q0-9
=2. f
VCO
V
CO
÷ 2 (Low frequency range).
f
REF
=f
Q0-9
=4.f
VCO
MR/OE
0
Outputs enabled (active)
Outputs disabled (high-impedance state) and
reset of the device. During reset the PLL
feedback loop is open. The VCO is tied to its
lowest frequency. The length of the reset
pulse should be greater than one reference
clock cycle (PCLK).
Note: 1 PLL operation requires BYPASS=1 and PLL_EN=1.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ASM5I9658 | 3.3V 1:10 LVCMOS PLL Clock Generator |
| ASM5I9658-32-ER | 3.3V 1:10 LVCMOS PLL Clock Generator |
| ASM5I9772A | 2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
| ASM5I9772A-52-ER | 2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
| ASM5I9772A-52-ET | 2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ASM5I9772A | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
| ASM5I9772A-52-ER | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
| ASM5I9772A-52-ET | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
| ASM5I9772AG-52-ER | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
| ASM5I9772AG-52-ET | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
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