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參數(shù)資料
| 型號(hào)： | ASM5I9772A |
| 廠商： | Alliance Semiconductor Corporation |
| 英文描述： | 2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
| 中文描述： | 2.5V或3.3V，200兆赫，12路輸出零延遲緩沖器 |
| 文件頁(yè)數(shù)： | 1/15頁(yè) |
| 文件大?。?/td> | 583K |
| 代理商： | ASM5I9772A |
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June 2005
rev 0.3
ASM5I9772A
Alliance Semiconductor
2575, Augustine Drive
Santa Clara, CA
Tel: 408.855.4900
Fax: 408.855.4999
www.alsc.com
Notice: The information in this document is subject to change without notice.
2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer
Features
Output frequency range: 8.33 MHz to 200 MHz
Input frequency range: 6.25 MHz to 125 MHz
2.5V or 3.3V operation
Split 2.5V/3.3V outputs
±2% max Output duty cycle variation
12 clock outputs: drive up to 24 clock lines
One feedback output
Three reference clock inputs: crystal or LVCMOS
300pS max output-output skew
Phase-locked loop (PLL) bypass mode
‘SpreadTrak’
Output enable/disable
Pin-compatible with CY29772, MPC9772 and MPC972
Industrial temperature range: –40°C to +85°C
52 pin 1.0 mm TQFP package
RoHS Compliance
Functional Description
The ASM5I9772A is a low-voltage high-performance
200 MHz PLL-based zero delay buffer, designed for high-
speed clock-distribution applications.
The ASM5I9772A features one on-chip crystal oscillator
and two LVCMOS reference clock inputs and provides 12
outputs partitioned in three banks of four outputs each.
Each bank divides the VCO output per SEL(A:C) settings,
see
Functional Table
.
These dividers allow output to input ratios of 8:1, 6:1, 5:1,
4:1, 3:1, 8:3, 5:2, 2:1, 5:3, 3:2, 4:3, 5:4, 1:1, and 5:6. Each
LVCMOS-compatible output can drive 50
series or
parallel-terminated
transmission
terminated transmission lines, each output can drive one or
two traces, giving the device an effective fanout of 1:24.
lines.
For
series-
The PLL is ensured stable given that the VCO is configured
to run between 200 MHz and 500 MHz. This allows a wide
range of output frequencies from 8 MHz to 200 MHz. For
normal operation, the external feedback input, FB_IN, is
connected to the feedback output, FB_OUT. The internal
VCO is running at multiples of the input reference clock set
by the feedback divider, see
Frequency Table.
When PLL_EN is LOW, PLL is bypassed and the reference
clock directly feeds the output dividers. This mode is fully
static and the minimum input clock frequency specification
does not apply.
Block Diagram
Sync
Frz
Sync
Frz
Sync
Frz
Sync
Frz
Sync
Frz
Sync
Frz
D Q
D Q
D Q
D Q
D Q
D Q
0
1
/2
Output Disable
Circuitry
12
Power-On
Reset
0
1
VCO
Phase
Detector
LPF
0
1
/4,/6,/8,/12
/4,/6,/8,/10
/2/4,/6,/8
/4,/6,/8,/10
Sync Pulse
Data Generator
2
2
2
2
XIN
XOUT
VCO_SEL
PLL_EN
REF_SEL
TCLK0
TCLK1
TCLK_SEL
FB_IN
FB_SEL2
MR#/OE
SELA(0,1)
SELB(0,1)
SELC(0,1)
FB_SEL(0,1)
SCLK
SDATA
INV_CLK
SYNC
FB_OUT
QC3
QC2
QC1
QC0
QB3
QB2
QB1
QB0
QA3
QA2
QA1
QA0
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ASM5I9772A-52-ER | 2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
| ASM5I9772A-52-ET | 2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
| ASM5I9772AG-52-ER | 2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
| ASM5I9772AG-52-ET | 2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
| ASM5I9773A | 2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ASM5I9772A-52-ER | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
| ASM5I9772A-52-ET | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
| ASM5I9772AG-52-ER | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
| ASM5I9772AG-52-ET | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
| ASM5I9773A | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
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