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參數(shù)資料
| 型號(hào)： | ASM5I9658G-32-LR |
| 廠商： | ALLIANCE SEMICONDUCTOR CORP |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | 3.3V 1:10 LVCMOS PLL Clock Generator |
| 中文描述： | 9658 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封裝： | 7 X 7 MM, GREEN, LQFP-32 |
| 文件頁(yè)數(shù)： | 8/14頁(yè) |
| 文件大?。?/td> | 579K |
| 代理商： | ASM5I9658G-32-LR |
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July 2005
rev 0.2
supply filter schemes discussed in this section should be
adequate to eliminate power supply noise related
problems in most designs.
ASM5I9658
3.3V 1:10 LVCMOS PLL Clock Generator
8 of
14
Notice: The information in this document is subject to change without notice.
Using the ASM5I9658 in zero-delay applications
Nested clock trees are typical applications for the
ASM5I9658. Designs using the ASM5I9658, as LVCMOS
PLL fanout buffer with zero insertion delay will show
significantly lower clock skew than clock distributions
developed from CMOS fanout buffers. The external
feedback option of the ASM59658 clock driver allows for
its use as a zero delay buffer. The PLL aligns the
feedback clock output edge with the clock input reference
edge resulting a near zero delay through the device (the
propagation delay through the device is virtually
eliminated). The maximum insertion delay of the device in
zero-delay applications is measured between the
reference clock input and any output. This effective delay
consists of the static phase offset, I/O jitter (phase or
long-term jitter), feedback path delay and the output-to-
output skew error relative to the feedback output.
Calculation of part-to-part skew
The ASM5I9658 zero delay buffer supports applications
where critical clock signal timing can be maintained
across several devices. If the reference clock inputs of
two or more ASM5I9658 are connected together, the
maximum overall timing uncertainty from the common
PCLK input to any output is:
t
SK(PP)
= t
(
φ
)
+ t
SK(O)
+ t
PD
, LINE(FB) + t
JIT(
φ
)
_ CF
This
components: static phase offset, output skew, feedback
board trace delay and I/O (phase) jitter:
maximum
timing
uncertainty
consist
of
4
Figure 4. ASM5I9658 max device-to-device skew
Due to the statistical nature of I/O jitter a RMS value (1
σ
)
is specified. I/O jitter numbers for other confidence factors
(CF) can be derived from Table 8.
Table 8: Confidence Factor CF
Probability of clock edge within the
distribution
± 1
σ
0.68268948
± 2
σ
0.95449988
± 3
σ
0.99730007
± 4
σ
0.99993663
± 5
σ
0.99999943
± 6
σ
0.99999999
The feedback trace delay is determined by the board
layout and can be used to fine-tune the effective delay
through each device. In the following example calculation
a I/O jitter confidence factor of 99.7% (
±3
σ
) is assumed,
resulting in a worst case timing uncertainty from input to
any output of -214 pS to 224 pS relative to PCLK
CF
(f
REF
= 100 MHz, FB=÷4, t
jit(
φ
)
=8 pS RMS at f
VCO
= 400
MHz):
t
SK(PP)
= [–70pS...80pS] + [–120pS...120pS] +
[(8pS _ –3)...(8pS _ 3)] + t
PD
, LINE(FB)
t
SK(PP)
= [–214pS...224pS] + t
PD
, LINE(FB)
Due to the frequency dependence of the I/O jitter, Figure
5. can be used for a more precise timing performance
analysis.
Figure 5. Maximum I/O Jitter versus frequency
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ASM5I9658 | 3.3V 1:10 LVCMOS PLL Clock Generator |
| ASM5I9658-32-ER | 3.3V 1:10 LVCMOS PLL Clock Generator |
| ASM5I9772A | 2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
| ASM5I9772A-52-ER | 2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
| ASM5I9772A-52-ET | 2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ASM5I9772A | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
| ASM5I9772A-52-ER | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
| ASM5I9772A-52-ET | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
| ASM5I9772AG-52-ER | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
| ASM5I9772AG-52-ET | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
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