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參數(shù)資料
| 型號(hào)： | AS4DDR16M72-8/XT |
| 廠商： | AUSTIN SEMICONDUCTOR INC |
| 元件分類： | DRAM |
| 英文描述： | 16M X 72 DDR DRAM, 0.8 ns, PBGA219 |
| 封裝： | 32 X 25 MM, PLASTIC, BGA-219 |
| 文件頁數(shù)： | 7/19頁 |
| 文件大?。?/td> | 363K |
| 代理商： | AS4DDR16M72-8/XT |
iiiiiPEM
PEM
1.2 G
1.2 Gbbbbb SDRAM-DDR
SDRAM-DDR
AS4DDR16M72PBG
AS4DDR16M72PBG
Rev. 2.1 06/09
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
15
Austin Semiconductor, Inc.
NOTES:
1. All voltages referenced to VSS.
2. Tests for AC timing, ICC, and electrical AC and DC characteristics may be
conducted at nominal reference/supply voltage levels, but the related
specifications and device operation are guaranteed for the full voltage
range specified.
3. Outputs measured with equivalent load:
4. AC timing and ICC tests may use a VIL-to-VIH swing of up to 1.5V in the test
environment, but input timing is still referenced to VREF (or to the crossing
point for CLK/CLK#), and parameter specifications are guaranteed for the
specified AC input levels under normal use conditions. The minimum slew
rate for the input signals used to test the device is 1V/ns in the range
between VIL(AC) and VIH(AC).
5. The AC and DC input level specifications are as defined in the SSTL_2
Standard (i.e., the receiver will effectively switch as a result of the signal
crossing the AC input level, and will remain in that state as long as the
signal does not ring back above [below] the DC input LOW [HIGH] level).
6. VREF is expected to equal VCCQ/2 of the transmitting device and to track
variations in the DC level of the same. Peak-to-peak noise (noncommon
mode) on VREF may not exceed ±2 percent of the DC value. Thus, from
VCCQ/2, VREF is allowed ±25mV for DC error and an additional ±25mV for
AC noise. This measurement is to be taken at the nearest VREF by-pass
capacitor.
7. VTT is not applied directly to the device. VTT is a system supply for signal
termination resistors, is expected to be set equal to VREF and must track
variations in the DC level of VREF.
8. VID is the magnitude of the difference between the input level on CLK and
the input level on CLK#.
9. The value of VIX and VMP are expected to equal VCCQ/2 of the transmitting
device and must track variations in the DC level of the same.
10. ICC is dependent on output loading and cycle rates. Specified values are
obtained with minimum cycle time with the outputs open.
11. Enables on-chip refresh and address counters.
12. ICC specifications are tested after the device is properly initialized, and is
averaged at the defined cycle rate.
13. This parameter is not tested but guaranteed by design. tA = 25OC, f = 1
MHz
14. Command/Address input slew rate = 0.5V/ns. For 266 MHz with slew rates
1V/ns and faster, tIS and tIH are reduced to 900ps. If the slew rate is less
than 0.5V/ns, timing must be derated: tIS has an additional 50ps per each
100mV/ns reduction in slew rate from the 500mV/ns. tIH has 0ps added,
that is, it remains constant. If the level, slew rate exceeds 4.5V/ns,
functionality is uncertain.
VTT
50
Ω
Reference
Output
Point
30pF
(VOUT)
15. The CLK/CLK# input reference level (for timing referenced to CLK/CLK#)
is the point at which CLK and CLK# cross; the input reference level for
signals other than CLK/CLK# is VREF.
16. Inputs are not recognized as valid until VREF stabilizes. Exception: during the
period before VREF stablizes, CKE < 0.3 x VCCQ is recognized as LOW.
17. The output timing reference level, as measured at the timing reference
point indicated in Note 3, is VTT.
18. tHZ and tLZ transitions occur in the same access time windows as valid
data transitions. These parameters are not referenced to a specific voltage
level, but specify when the device output is no longer driving (HZ) or
begins driving (LZ).
19. The maximum limit for this parameter is not a device limit. The device will
operate with a greater value for this parameter, but system performance
(bus turnaround) will degrade accordingly.
20. This is not a device limit. The device will operate with a negative value, but
system performance could be degraded due to bus turnaround.
21. It is recommended that DQS be valid (HIGH or LOW) on or before the
WRITE command. The case shown (DQS going from High-Z to logic LOW)
applies when no WRITEs were previously in progress on the bus. If a
previous WRITE was in progress, DQS could be HIGH during this time,
depending on tDQSS.
22. MIN (tRC or tRFC) for ICC measurements is the smallest multiple of tCK that
meets the minimum absolute value for the respective parameter. tRAS
(MAX) for ICC measurements is the largest multiple of tCK that meets the
maximum absolute value for tRAS.
23. The refresh period 64ms. This equates to an average refresh rate of
However, an AUTO REFRESH command must be asserted at least once
every 70.3s; burst refreshing or posting by the DRAM controller greater
than eight refresh cycles is not allowed.
24. The I/O capacitance per DQS and DQ byte/group will not differ by more
than this maximum amount for any given device.
25. The valid data window is derived by achieving other specifications - tHP
(tCK/2), tDQSQ, and tQH (tQH = tHP - tQHS). The data valid window derates
directly porportional with the clock duty cycle and a practical data valid
window can be derived. The clock is allowed a maximum duty cycle
variation of 45/55. Functionality is uncertain when operating beyond a
45/55 ratio. The data valid window derating curves are provided
26. Referenced to each output group: LDQS with DQ0-DQ7; and UDQS with
DQ8-DQ15 of each chip.
27. This limit is actually a nominal value and does not result in a fail value.
CKE is HIGH below for duty cycles ranging between 50/50 and 45/55.
during REFRESH command period (tRFC [MIN]) else CKE is LOW (i.e.,
during standby)
28. To maintain a valid level, the transitioning edge of the input must:
a) Sustain a constant slew rate from the current AC level through to the
target AC level, VIL(AC) or VIH(AC).
b) Reach at least the target AC level.
c) After the AC target level is reached, continue to maintain at least the
target DC level, VIL(DC) or VIH(DC).
160
0
Maximum
Nominal high
Nominal low
Minimum
Nominal high
Nominal low
Minimum
Maximum
-20
140
-40
120
-60
-80
IOUT
(mA)
IOUT
(mA) -100
-120
-140
40
-160
20
-180
0
-200
0.0
0.5
1.0
1.5
2.0
2.5
0.0
0.5
1.0
1.5
2.0
2.5
VOUT (V)
VCCQ - VOUT (V)
100
80
60
FIGURE A - PULL-DOWN CHARACTERISTICS
FIGURE B - PULL-UP CHARACTERISTICS
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AS4DDR16M72PBG | 制造商:AUSTIN 制造商全稱:Austin Semiconductor 功能描述:16Mx72 DDR SDRAM iNTEGRATED Plastic Encapsulated Microcircuit |
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| AS4DDR16M72PBG-10/IT | 制造商:Micross Components 功能描述:SDRAM-DDR, 1.2GB - Trays |
| AS4DDR16M72PBG-10/XT | 制造商:Micross Components 功能描述:SDRAM-DDR, 1.2GB - Trays |
| AS4DDR16M72PBG-75/IT | 制造商:Micross Components 功能描述:SDRAM-DDR, 1.2GB - Trays |
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